MGT_quad_gen Entity Reference

MGT quad generation. More...

Inheritance diagram for MGT_quad_gen:

Entities
Behavioral	architecture
	MGT quad generation. More...

Libraries
IEEE
xil_defaultlib

Use Clauses
STD_LOGIC_1164
mgt_type	Package <mgt_type>

Generics
num_quad_tx_rx	natural := 1

Ports
TTC_CLK	in	std_logic
MGT_CLK_GTREFCLK_PAD_N_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
MGT_CLK_GTREFCLK_PAD_P_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
mgt_TXUSRCLK_OUT	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
mgt_RXUSRCLK_OUT	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
mgt_SOFT_RESET_TX_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
mgt_SOFT_RESET_RX_IN	in	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
RXN_IN	in	mgt_rx_array ( num_quad_tx_rx- 1 downto 0 )
RXP_IN	in	mgt_rx_array ( num_quad_tx_rx- 1 downto 0 )
TXN_IN	out	mgt_tx_array ( num_quad_tx_rx- 1 downto 0 )
TXP_IN	out	mgt_tx_array ( num_quad_tx_rx- 1 downto 0 )
rxdata_quad_array	out	mgt_rxdata_array ( num_quad_tx_rx- 1 downto 0 )
txdata_quad_array	in	mgt_txdata_array ( num_quad_tx_rx- 1 downto 0 )
mgt_TX_FSM_RESET_DONE	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
mgt_RX_FSM_RESET_DONE	out	std_logic_vector ( 4 * num_quad_tx_rx- 1 downto 0 )
rxbyteisaligned_quad_array	out	mgt_rxbyteisaligned_array ( num_quad_tx_rx- 1 downto 0 )
rxresetdone_quad_array	out	mgt_rxresetdone_array ( num_quad_tx_rx- 1 downto 0 )
txresetdone_quad_array	out	mgt_txresetdone_array ( num_quad_tx_rx- 1 downto 0 )
gt_rxpd_array	in	mgt_rxpd_array ( num_quad_tx_rx- 1 downto 0 )
gt_txpd_array	in	mgt_txpd_array ( num_quad_tx_rx- 1 downto 0 )
loopback_quad_array	in	mgt_loopback_array ( num_quad_tx_rx- 1 downto 0 )
rxchariscomma_quad_array	out	mgt_rxchariskcomm_array ( num_quad_tx_rx- 1 downto 0 )
rxcharisk_quad_array	out	mgt_rxcharisk_array ( num_quad_tx_rx- 1 downto 0 )
txcharisk_quad_array	in	mgt_txcharisk_array ( num_quad_tx_rx- 1 downto 0 )
txbufstatus_quad_array	out	mgt_txbufstatus_array ( num_quad_tx_rx- 1 downto 0 )
rxbyterealign_quad_array	out	mgt_rxbyterealign_array ( num_quad_tx_rx- 1 downto 0 )
rxcommadet_quad_array	out	mgt_rxcommadet_array ( num_quad_tx_rx- 1 downto 0 )
rxdisperr_quad_array	out	mgt_rxdisperr_array ( num_quad_tx_rx- 1 downto 0 )
rxnotintable_quad_array	out	mgt_rxnotintable_array ( num_quad_tx_rx- 1 downto 0 )
gt0_cpllfbclklost_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
gt0_cplllock_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
gt1_cpllfbclklost_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
gt1_cplllock_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
gt2_cpllfbclklost_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
gt2_cplllock_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
gt3_cpllfbclklost_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )
gt3_cplllock_out	out	std_logic_vector ( num_quad_tx_rx- 1 downto 0 )

Detailed Description

MGT quad generation.

MGT_quad_gen generates num_quad_tx_rx MGT quads that contain both transmitters and receivers. This is done via an intermediate 'mgt_tx_rx_6g4_wrapper' level of hierarchy that ties off unused signals and thus simplifies the interface to the MGTs at this level. The transceiver and receiver in each MGT operate independently of each other: they do not comprise a duplex link. They are grouped together in the VHDL only because they are co-located in the same MGT.

On the receive path, this component performs the following functions:

• Receives 1 quad × 6.4.2 Gb/s serial data streams from Hub through the back plane
  
• Decodes the data using the 8b/10b line code;
• Recovers a 160 MHz clock from the data;
• Converts each serial data stream to parallel data, 32 bits wide, synchronous with the recovered 160 MHz clock;
• Performs word-alignment of the output data to the 280 MHz clock (such that bit 0 of each 32-bit word is located in the correct place)
• Outputs, for each of the 16 32-bit data outputs, a signal indicating when a comma has been received (the signal COMMADET from the Xilinx MGT block).

The MGTs here are implemented using Xilinx IP. MGT settings:

• Transceiver: GTH
  • Line rate (Tx and Rx): 6.4 Gb/s
  • Reference clock (Tx and Rx): 160 MHz
  • External data width: 32 bits
  • Encoding/decoding scheme: 8b/10b
  • Comma value = K28.5

    Author

    Mohammed Syiad

Definition at line 34 of file mgt_quad_gen.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd