Behavioral Architecture Reference

MGT quad generation. More...

Signals
RXN_IN_tx_rx	mgt_rx_array ( num_quad_tx_rx- 1 downto 0 )
RXP_IN_tx_rx	mgt_rx_array ( num_quad_tx_rx- 1 downto 0 )
TXN_IN_tx_rx	mgt_tx_array ( num_quad_tx_rx- 1 downto 0 )
TXP_IN_tx_rx	mgt_tx_array ( num_quad_tx_rx- 1 downto 0 )

Instantiations
mgt_quad_rx_tx	mgt_tx_rx_6g4_wrapper <Entity mgt_tx_rx_6g4_wrapper>

Detailed Description

MGT quad generation.

MGT_quad_gen generates num_quad_tx_rx MGT quads that contain both transmitters and receivers. This is done via an intermediate 'mgt_tx_rx_6g4_wrapper' level of hierarchy that ties off unused signals and thus simplifies the interface to the MGTs at this level. The transceiver and receiver in each MGT operate independently of each other: they do not comprise a duplex link. They are grouped together in the VHDL only because they are co-located in the same MGT.

On the receive path, this component performs the following functions:

• Receives 1 quad × 6.4.2 Gb/s serial data streams from Hub through the back plane
  
• Decodes the data using the 8b/10b line code;
• Recovers a 160 MHz clock from the data;
• Converts each serial data stream to parallel data, 32 bits wide, synchronous with the recovered 160 MHz clock;
• Performs word-alignment of the output data to the 280 MHz clock (such that bit 0 of each 32-bit word is located in the correct place)
• Outputs, for each of the 16 32-bit data outputs, a signal indicating when a comma has been received (the signal COMMADET from the Xilinx MGT block).

The MGTs here are implemented using Xilinx IP. MGT settings:

• Transceiver: GTH
  • Line rate (Tx and Rx): 6.4 Gb/s
  • Reference clock (Tx and Rx): 160 MHz
  • External data width: 32 bits
  • Encoding/decoding scheme: 8b/10b
  • Comma value = K28.5

    Author

    Mohammed Syiad

Definition at line 89 of file mgt_quad_gen.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_quad_gen.vhd