eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt_quad_gen.vhd
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1 
26 
27 
28 library IEEE;
29 use IEEE.STD_LOGIC_1164.ALL;
30 library xil_defaultlib;
31 use work.mgt_type.all;
32 
34 entity MGT_quad_gen is
35 generic( num_quad_tx_rx: natural := 1
36  );
37  Port (
38  --refclk160 : IN std_logic;
39  TTC_CLK : IN std_logic;
40  MGT_CLK_GTREFCLK_PAD_N_IN : IN std_logic_vector(num_quad_tx_rx-1 downto 0);
41  MGT_CLK_GTREFCLK_PAD_P_IN : IN std_logic_vector(num_quad_tx_rx-1 downto 0);
42 
43  mgt_TXUSRCLK_OUT : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
44  mgt_RXUSRCLK_OUT : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
45 
46  mgt_SOFT_RESET_TX_IN : in std_logic_vector(num_quad_tx_rx -1 downto 0);
47  mgt_SOFT_RESET_RX_IN : in std_logic_vector(num_quad_tx_rx -1 downto 0);
48  -- data
49  RXN_IN : IN mgt_rx_array(num_quad_tx_rx-1 downto 0);
50  RXP_IN : IN mgt_rx_array(num_quad_tx_rx-1 downto 0);
51  TXN_IN : OUT mgt_tx_array(num_quad_tx_rx-1 downto 0);
52  TXP_IN : OUT mgt_tx_array(num_quad_tx_rx-1 downto 0);
53 
54  rxdata_quad_array : out mgt_rxdata_array (num_quad_tx_rx -1 downto 0);
55  txdata_quad_array : in mgt_txdata_array (num_quad_tx_rx -1 downto 0);
56  -- status and monitoring
57  mgt_TX_FSM_RESET_DONE : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
58  mgt_RX_FSM_RESET_DONE : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
59  rxbyteisaligned_quad_array : out mgt_rxbyteisaligned_array(num_quad_tx_rx -1 downto 0);
60  rxresetdone_quad_array : out mgt_rxresetdone_array (num_quad_tx_rx -1 downto 0);
61  txresetdone_quad_array : out mgt_txresetdone_array (num_quad_tx_rx -1 downto 0);
62 
63  gt_rxpd_array : in mgt_rxpd_array (num_quad_tx_rx -1 downto 0);
64  gt_txpd_array : in mgt_txpd_array (num_quad_tx_rx -1 downto 0);
65  loopback_quad_array : in mgt_loopback_array (num_quad_tx_rx-1 downto 0);
66  rxchariscomma_quad_array : out mgt_rxchariskcomm_array (num_quad_tx_rx -1 downto 0);
67  rxcharisk_quad_array : out mgt_rxcharisk_array (num_quad_tx_rx -1 downto 0);
68  txcharisk_quad_array : in mgt_txcharisk_array (num_quad_tx_rx -1 downto 0);
69  txbufstatus_quad_array : out mgt_txbufstatus_array (num_quad_tx_rx -1 downto 0);
70  rxbyterealign_quad_array : out mgt_rxbyterealign_array (num_quad_tx_rx -1 downto 0);
71  rxcommadet_quad_array : out mgt_rxcommadet_array (num_quad_tx_rx -1 downto 0);
72  rxdisperr_quad_array : out mgt_rxdisperr_array (num_quad_tx_rx -1 downto 0);
73  rxnotintable_quad_array : out mgt_rxnotintable_array (num_quad_tx_rx -1 downto 0);
74 -- mgt_QPLLREFCLKLOST_OUT : out std_logic_vector(num_quad_tx_rx-1 downto 0) ;
75 -- mgt_QPLLLOCK_OUT : out std_logic_vector (num_quad_tx_rx -1 downto 0);
76  gt0_cpllfbclklost_out : out std_logic_vector(num_quad_tx_rx -1 downto 0) ;
77  gt0_cplllock_out : out std_logic_vector(num_quad_tx_rx -1 downto 0) ;
78  gt1_cpllfbclklost_out : out std_logic_vector(num_quad_tx_rx -1 downto 0) ;
79  gt1_cplllock_out : out std_logic_vector(num_quad_tx_rx -1 downto 0) ;
80  gt2_cpllfbclklost_out : out std_logic_vector(num_quad_tx_rx -1 downto 0) ;
81  gt2_cplllock_out : out std_logic_vector(num_quad_tx_rx -1 downto 0) ;
82  gt3_cpllfbclklost_out : out std_logic_vector(num_quad_tx_rx -1 downto 0) ;
83  gt3_cplllock_out : out std_logic_vector(num_quad_tx_rx -1 downto 0)
84 
85  );
86 
87 end MGT_quad_gen;
89 architecture Behavioral of MGT_quad_gen is
90 
91 
92 
93 signal RXN_IN_tx_rx,RXP_IN_tx_rx : mgt_rx_array (num_quad_tx_rx -1 downto 0);
94 signal TXN_IN_tx_rx,TXP_IN_tx_rx : mgt_tx_array (num_quad_tx_rx -1 downto 0);
95 
96 
97 begin
98 
99 
100 
101 
102 
103 
104 
105 MGT_GEN: for i in 0 to num_quad_tx_rx-1
106 
107 generate
108 
109 mgt_quad_Rx_Tx: entity work.mgt_tx_rx_6g4_wrapper
110 
111  -- This part will generate n quads, n*4 = 4n mgts.
112 
113  Port map (
114 
115  SOFT_RESET_TX_IN => mgt_SOFT_RESET_TX_IN(i),
116  SOFT_RESET_RX_IN => mgt_SOFT_RESET_RX_IN(i),
117  RXN_IN => RXN_IN(i).RXN_IN ,
118  RXP_IN => RXP_IN(i).RXP_IN,
119  TXN_OUT => TXN_IN(i).TXN_OUT,
120  TXP_OUT => TXP_IN(i).TXP_OUT,
121  Q0_CLK0_GTREFCLK_PAD_N_IN => MGT_CLK_GTREFCLK_PAD_N_IN(i) ,
122  Q0_CLK0_GTREFCLK_PAD_P_IN => MGT_CLK_GTREFCLK_PAD_P_IN(i) ,
123 
124  GT0_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(i+3*i),
125  GT0_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(i+3*i),
126  GT1_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(i+1+3*i),
127  GT1_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(i+1+3*i),
128  GT2_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(i+2+3*i),
129  GT2_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(i+2+3*i),
130  GT3_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(i+3+3*i),
131  GT3_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(i+3+3*i),
132 
133  GT0_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(i+3*i),
134  GT0_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(i+3*i),
135  GT1_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(i+1+3*i),
136  GT1_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(i+1+3*i),
137  GT2_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(i+2+3*i) ,
138  GT2_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(i+2+3*i),
139  GT3_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(i+3+3*i) ,
140  GT3_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(i+3+3*i),
141 
142  gt0_cpllfbclklost_out => gt0_cpllfbclklost_out(i) ,
143  gt0_cplllock_out => gt0_cplllock_out(i) ,
144  gt1_cpllfbclklost_out => gt1_cpllfbclklost_out(i) ,
145  gt1_cplllock_out => gt1_cplllock_out(i) ,
146  gt2_cpllfbclklost_out => gt2_cpllfbclklost_out(i) ,
147  gt2_cplllock_out => gt2_cplllock_out(i) ,
148  gt3_cpllfbclklost_out => gt3_cpllfbclklost_out(i) ,
149  gt3_cplllock_out => gt3_cplllock_out(i) ,
150 
151  --_________________________________________________________________________
152  --GT0 (X0Y0)
153  --____________________________CHANNEL PORTS________________________________
154 
155  gt0_loopback_in => loopback_quad_array(i).gt0_loopback_in,
156  gt0_rxpd_in => gt_rxpd_array(i).gt0_rxpd,
157  gt0_txpd_in => gt_txpd_array(i).gt0_txpd,
158  gt0_rxdata_out => rxdata_quad_array (i).gt0_rxdata_out,
159  gt0_rxdisperr_out => rxdisperr_quad_array(i).gt0_rxdisperr,
160  gt0_rxnotintable_out => rxnotintable_quad_array(i).gt0_rxnotintable,
161  gt0_rxbyterealign_out => rxbyterealign_quad_array(i).gt0_rxbyterealign,
162  gt0_rxcommadet_out => rxcommadet_quad_array(i).gt0_rxcommadet,
163  gt0_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt0_rxbyteisaligned,
164  gt0_rxchariscomma_out => rxchariscomma_quad_array(i).gt0_rxchariscomma_out,
165  gt0_rxcharisk_out => rxcharisk_quad_array(i).gt0_rxcharisk_out,
166  gt0_rxresetdone_out => rxresetdone_quad_array(i).gt0_rxresetdone,
167  gt0_txdata_in => txdata_quad_array(i).gt0_txdata_in ,
168  gt0_txresetdone_out => txresetdone_quad_array(i).gt0_txresetdone,
169  gt0_txcharisk_in => txcharisk_quad_array (i).gt0_txcharisk,
170  gt0_txbufstatus_out => txbufstatus_quad_array(i).gt0_txbufstatus,
171 
172  --GT1 (X0Y1)
173  --____________________________CHANNEL PORTS________________________________
174  gt1_loopback_in => loopback_quad_array(i).gt0_loopback_in,
175  gt1_rxpd_in => gt_rxpd_array(i).gt1_rxpd,
176  gt1_txpd_in => gt_txpd_array(i).gt1_txpd,
177  gt1_rxdata_out => rxdata_quad_array (i).gt1_rxdata_out,
178  gt1_rxdisperr_out => rxdisperr_quad_array(i).gt1_rxdisperr,
179  gt1_rxnotintable_out => rxnotintable_quad_array(i).gt1_rxnotintable,
180  gt1_rxbyterealign_out => rxbyterealign_quad_array(i).gt1_rxbyterealign,
181  gt1_rxcommadet_out => rxcommadet_quad_array(i).gt1_rxcommadet,
182  gt1_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt1_rxbyteisaligned,
183  gt1_rxchariscomma_out => rxchariscomma_quad_array(i).gt1_rxchariscomma_out,
184  gt1_rxcharisk_out => rxcharisk_quad_array(i).gt1_rxcharisk_out,
185  gt1_rxresetdone_out => rxresetdone_quad_array(i).gt1_rxresetdone,
186  gt1_txdata_in => txdata_quad_array(i).gt1_txdata_in,
187  gt1_txresetdone_out => txresetdone_quad_array(i).gt1_txresetdone,
188  gt1_txcharisk_in => txcharisk_quad_array (i).gt1_txcharisk,
189  gt1_txbufstatus_out => txbufstatus_quad_array(i).gt1_txbufstatus,
190  --GT2 (X0Y2)
191  --____________________________CHANNEL PORTS________________________________
192  gt2_loopback_in => loopback_quad_array(i).gt0_loopback_in,
193  gt2_rxpd_in => gt_rxpd_array(i).gt2_rxpd,
194  gt2_txpd_in => gt_txpd_array(i).gt2_txpd,
195  gt2_rxdata_out => rxdata_quad_array (i).gt2_rxdata_out,
196  gt2_rxdisperr_out => rxdisperr_quad_array(i).gt2_rxdisperr,
197  gt2_rxnotintable_out => rxnotintable_quad_array(i).gt2_rxnotintable,
198  gt2_rxbyterealign_out => rxbyterealign_quad_array(i).gt2_rxbyterealign,
199  gt2_rxcommadet_out => rxcommadet_quad_array(i).gt2_rxcommadet,
200  gt2_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt2_rxbyteisaligned,
201  gt2_rxchariscomma_out => rxchariscomma_quad_array(i).gt2_rxchariscomma_out,
202  gt2_rxcharisk_out => rxcharisk_quad_array(i).gt2_rxcharisk_out,
203  gt2_rxresetdone_out => rxresetdone_quad_array(i).gt2_rxresetdone,
204  gt2_txdata_in => txdata_quad_array(i).gt2_txdata_in,
205  gt2_txresetdone_out => txresetdone_quad_array(i).gt2_txresetdone,
206  gt2_txcharisk_in => txcharisk_quad_array (i).gt2_txcharisk,
207  gt2_txbufstatus_out => txbufstatus_quad_array(i).gt2_txbufstatus,
208 
209  --GT3 (X0Y3)
210  --____________________________CHANNEL PORTS________________________________
211  gt3_loopback_in => loopback_quad_array(i).gt0_loopback_in,
212  gt3_rxpd_in => gt_rxpd_array(i).gt3_rxpd,
213  gt3_txpd_in => gt_txpd_array(i).gt3_txpd,
214  gt3_rxdata_out => rxdata_quad_array (i).gt3_rxdata_out,
215  gt3_rxdisperr_out => rxdisperr_quad_array(i).gt3_rxdisperr,
216  gt3_rxnotintable_out => rxnotintable_quad_array(i).gt3_rxnotintable,
217  gt3_rxbyterealign_out => rxbyterealign_quad_array(i).gt3_rxbyterealign,
218  gt3_rxcommadet_out => rxcommadet_quad_array(i).gt3_rxcommadet,
219  gt3_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt3_rxbyteisaligned,
220  gt3_rxchariscomma_out => rxchariscomma_quad_array(i).gt3_rxchariscomma_out,
221  gt3_rxcharisk_out => rxcharisk_quad_array(i).gt3_rxcharisk_out,
222  gt3_rxresetdone_out => rxresetdone_quad_array(i).gt3_rxresetdone,
223  gt3_txdata_in => txdata_quad_array(i).gt3_txdata_in,
224  gt3_txresetdone_out => txresetdone_quad_array(i).gt3_txresetdone,
225  gt3_txcharisk_in => txcharisk_quad_array (i).gt3_txcharisk,
226  gt3_txbufstatus_out => txbufstatus_quad_array(i).gt3_txbufstatus,
227 
228  --____________________________COMMON PORTS________________________________
229  --GT0_QPLLLOCK_OUT => mgt_QPLLLOCK_OUT(i),--.GT0_QPLLLOCK_OUT,
230  --GT0_QPLLREFCLKLOST_OUT => mgt_QPLLREFCLKLOST_OUT(i),--.GT0_QPLLREFCLKLOST_OUT,
231  sysclk_in => TTC_CLK
232 
233  );
234 
235  end generate MGT_GEN;
236 
237 end Behavioral;
MGT_quad_gen.Behavioral
MGT quad generation.
Definition: mgt_quad_gen.vhd:89
MGT_quad_gen
MGT quad generation.
Definition: mgt_quad_gen.vhd:34
mgt_tx_rx_6g4_wrapper
mgt selection wrapper
Definition: mgt_tx_rx_6g4_wrapper.vhd:17
mgt_tx_rx_6g4_wrapper.gt1_rxdata_out
out gt1_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:128
mgt_tx_rx_6g4_wrapper.gt3_txbufstatus_out
out gt3_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:208
mgt_tx_rx_6g4_wrapper.gt3_rxbyteisaligned_out
out gt3_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:193
mgt_tx_rx_6g4_wrapper.gt2_txresetdone_out
out gt2_txresetdone_out std_logic
Transmit Ports - TX Fabric Clock Output Control Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:174
mgt_tx_rx_6g4_wrapper.gt1_txdata_in
in gt1_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:142
mgt_tx_rx_6g4_wrapper.GT0_TXUSRCLK_OUT
out GT0_TXUSRCLK_OUT std_logic
tx user clock out gt0
Definition: mgt_tx_rx_6g4_wrapper.vhd:56
mgt_tx_rx_6g4_wrapper.gt0_txbufstatus_out
out gt0_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:118
mgt_tx_rx_6g4_wrapper.TXN_OUT
out TXN_OUT std_logic_vector( 3 downto 0)
tx quad output
Definition: mgt_tx_rx_6g4_wrapper.vhd:34
mgt_tx_rx_6g4_wrapper.gt0_rxdisperr_out
out gt0_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:99
mgt_tx_rx_6g4_wrapper.GT3_TX_FSM_RESET_DONE_OUT
out GT3_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:52
mgt_tx_rx_6g4_wrapper.GT2_RX_FSM_RESET_DONE_OUT
out GT2_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:50
mgt_tx_rx_6g4_wrapper.gt2_rxresetdone_out
out gt2_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:170
mgt_tx_rx_6g4_wrapper.gt2_cplllock_out
out gt2_cplllock_out std_logic
gt2_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:82
mgt_tx_rx_6g4_wrapper.gt2_rxpd_in
in gt2_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:155
mgt_tx_rx_6g4_wrapper.gt1_txbufstatus_out
out gt1_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:148
mgt_tx_rx_6g4_wrapper.gt0_rxdata_out
out gt0_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:97
mgt_tx_rx_6g4_wrapper.GT2_TXUSRCLK_OUT
out GT2_TXUSRCLK_OUT std_logic
tx user clock out gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:64
mgt_tx_rx_6g4_wrapper.gt3_rxdisperr_out
out gt3_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:190
mgt_tx_rx_6g4_wrapper.gt2_loopback_in
in gt2_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:153
mgt_tx_rx_6g4_wrapper.gt2_cpllfbclklost_out
out gt2_cpllfbclklost_out std_logic
gt2_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:80
mgt_tx_rx_6g4_wrapper.gt1_rxresetdone_out
out gt1_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:140
mgt_tx_rx_6g4_wrapper.gt1_cpllfbclklost_out
out gt1_cpllfbclklost_out std_logic
gt1_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:76
mgt_tx_rx_6g4_wrapper.gt0_txdata_in
in gt0_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:112
mgt_tx_rx_6g4_wrapper.gt3_rxdata_out
out gt3_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:188
mgt_tx_rx_6g4_wrapper.gt2_rxbyteisaligned_out
out gt2_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:163
mgt_tx_rx_6g4_wrapper.gt0_cplllock_out
out gt0_cplllock_out std_logic
gt0_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:74
mgt_tx_rx_6g4_wrapper.GT1_RX_FSM_RESET_DONE_OUT
out GT1_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:46
mgt_tx_rx_6g4_wrapper.gt0_rxchariscomma_out
out gt0_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:106
mgt_tx_rx_6g4_wrapper.gt0_txresetdone_out
out gt0_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:114
mgt_tx_rx_6g4_wrapper.GT3_TXUSRCLK_OUT
out GT3_TXUSRCLK_OUT std_logic
tx user clock out gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:68
mgt_tx_rx_6g4_wrapper.GT3_RX_FSM_RESET_DONE_OUT
out GT3_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:54
mgt_tx_rx_6g4_wrapper.gt2_rxdisperr_out
out gt2_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:160
mgt_tx_rx_6g4_wrapper.gt0_rxresetdone_out
out gt0_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:109
mgt_tx_rx_6g4_wrapper.gt3_txdata_in
in gt3_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:202
mgt_tx_rx_6g4_wrapper.gt3_rxresetdone_out
out gt3_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:200
mgt_tx_rx_6g4_wrapper.gt2_txbufstatus_out
out gt2_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:178
mgt_tx_rx_6g4_wrapper.gt3_txcharisk_in
in gt3_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:206
mgt_tx_rx_6g4_wrapper.gt0_rxpd_in
in gt0_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:94
mgt_tx_rx_6g4_wrapper.gt2_rxchariscomma_out
out gt2_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:167
mgt_tx_rx_6g4_wrapper.GT3_RXUSRCLK_OUT
out GT3_RXUSRCLK_OUT std_logic
rx user clock out gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:70
mgt_tx_rx_6g4_wrapper.gt0_rxbyteisaligned_out
out gt0_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:102
mgt_tx_rx_6g4_wrapper.GT0_TX_FSM_RESET_DONE_OUT
out GT0_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt0
Definition: mgt_tx_rx_6g4_wrapper.vhd:40
mgt_tx_rx_6g4_wrapper.SOFT_RESET_TX_IN
in SOFT_RESET_TX_IN std_logic
soft reset of tx quad
Definition: mgt_tx_rx_6g4_wrapper.vhd:27
mgt_tx_rx_6g4_wrapper.GT1_RXUSRCLK_OUT
out GT1_RXUSRCLK_OUT std_logic
rx user clock out gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:62
mgt_tx_rx_6g4_wrapper.gt1_txresetdone_out
out gt1_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:144
mgt_tx_rx_6g4_wrapper.gt1_txcharisk_in
in gt1_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:146
mgt_tx_rx_6g4_wrapper.gt1_rxpd_in
in gt1_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:125
mgt_tx_rx_6g4_wrapper.gt1_rxbyteisaligned_out
out gt1_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:133
mgt_tx_rx_6g4_wrapper.RXN_IN
in RXN_IN std_logic_vector( 3 downto 0)
rx quad input
Definition: mgt_tx_rx_6g4_wrapper.vhd:31
mgt_tx_rx_6g4_wrapper.GT2_RXUSRCLK_OUT
out GT2_RXUSRCLK_OUT std_logic
rx user clock out gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:66
mgt_tx_rx_6g4_wrapper.gt1_rxchariscomma_out
out gt1_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:137
mgt_tx_rx_6g4_wrapper.gt2_rxdata_out
out gt2_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:158
mgt_tx_rx_6g4_wrapper.gt3_rxpd_in
in gt3_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:185
mgt_tx_rx_6g4_wrapper.Q0_CLK0_GTREFCLK_PAD_N_IN
in Q0_CLK0_GTREFCLK_PAD_N_IN std_logic
clock input to the quad
Definition: mgt_tx_rx_6g4_wrapper.vhd:37
mgt_tx_rx_6g4_wrapper.gt2_txcharisk_in
in gt2_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:176
mgt_tx_rx_6g4_wrapper.gt3_rxchariscomma_out
out gt3_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:197
mgt_tx_rx_6g4_wrapper.gt0_cpllfbclklost_out
out gt0_cpllfbclklost_out std_logic
gt0_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:72
mgt_tx_rx_6g4_wrapper.gt2_txdata_in
in gt2_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:172
mgt_tx_rx_6g4_wrapper.GT2_TX_FSM_RESET_DONE_OUT
out GT2_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:48
mgt_tx_rx_6g4_wrapper.gt1_loopback_in
in gt1_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:123
mgt_tx_rx_6g4_wrapper.gt3_cpllfbclklost_out
out gt3_cpllfbclklost_out std_logic
gt3_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:84
mgt_tx_rx_6g4_wrapper.gt1_cplllock_out
out gt1_cplllock_out std_logic
gt1_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:78
mgt_tx_rx_6g4_wrapper.gt0_txcharisk_in
in gt0_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:116
mgt_tx_rx_6g4_wrapper.GT0_RXUSRCLK_OUT
out GT0_RXUSRCLK_OUT std_logic
rx user clock out gt0
Definition: mgt_tx_rx_6g4_wrapper.vhd:58
mgt_tx_rx_6g4_wrapper.GT0_RX_FSM_RESET_DONE_OUT
out GT0_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gto
Definition: mgt_tx_rx_6g4_wrapper.vhd:42
mgt_tx_rx_6g4_wrapper.gt1_rxdisperr_out
out gt1_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:130
mgt_tx_rx_6g4_wrapper.gt3_txresetdone_out
out gt3_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:204
mgt_tx_rx_6g4_wrapper.SOFT_RESET_RX_IN
in SOFT_RESET_RX_IN std_logic
soft reset of rx quad
Definition: mgt_tx_rx_6g4_wrapper.vhd:29
mgt_tx_rx_6g4_wrapper.gt0_loopback_in
in gt0_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:92
mgt_tx_rx_6g4_wrapper.gt3_cplllock_out
out gt3_cplllock_out std_logic
gt3_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:86
mgt_tx_rx_6g4_wrapper.GT1_TX_FSM_RESET_DONE_OUT
out GT1_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:44
mgt_tx_rx_6g4_wrapper.GT1_TXUSRCLK_OUT
out GT1_TXUSRCLK_OUT std_logic
tx user clock out gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:60
mgt_type
Definition: mgt_type_pkg.vhd:4
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