eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt_tx_rx_6g4_wrapper.vhd
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1 
7 library ieee;
8 use ieee.std_logic_1164.all;
9 use ieee.numeric_std.all;
10 use ieee.std_logic_unsigned.all;
11 library UNISIM;
12 use UNISIM.VCOMPONENTS.ALL;
13 Library work;
14 Library xil_defaultlib;
15 
17 entity mgt_tx_rx_6g4_wrapper is
18 generic
19 (
20  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
21  STABLE_CLOCK_PERIOD : integer := 16
22 
23 );
24 port
25 (
27  SOFT_RESET_TX_IN : in std_logic;
29  SOFT_RESET_RX_IN : in std_logic;
31  RXN_IN : in std_logic_vector(3 downto 0);
32  RXP_IN : in std_logic_vector(3 downto 0);
34  TXN_OUT : out std_logic_vector(3 downto 0);
35  TXP_OUT : out std_logic_vector(3 downto 0);
37  Q0_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
38  Q0_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
40  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
42  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
44  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
46  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
48  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
50  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
52  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
54  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
56  GT0_TXUSRCLK_OUT : out std_logic;
58  GT0_RXUSRCLK_OUT : out std_logic;
60  GT1_TXUSRCLK_OUT : out std_logic;
62  GT1_RXUSRCLK_OUT : out std_logic;
64  GT2_TXUSRCLK_OUT : out std_logic;
66  GT2_RXUSRCLK_OUT : out std_logic;
68  GT3_TXUSRCLK_OUT : out std_logic;
70  GT3_RXUSRCLK_OUT : out std_logic;
72  gt0_cpllfbclklost_out : out std_logic;
74  gt0_cplllock_out : out std_logic;
76  gt1_cpllfbclklost_out : out std_logic;
78  gt1_cplllock_out : out std_logic;
80  gt2_cpllfbclklost_out : out std_logic;
82  gt2_cplllock_out : out std_logic;
84  gt3_cpllfbclklost_out : out std_logic;
86  gt3_cplllock_out : out std_logic;
87 
88  -- _________________________________________________________________________
89  --GT0 (X0Y0)
90  --____________________________CHANNEL PORTS________________________________
92  gt0_loopback_in : in std_logic_vector(2 downto 0);
94  gt0_rxpd_in : in std_logic_vector(1 downto 0);
95  gt0_txpd_in : in std_logic_vector(1 downto 0);
97  gt0_rxdata_out : out std_logic_vector(31 downto 0);
99  gt0_rxdisperr_out : out std_logic_vector(3 downto 0);
100  gt0_rxnotintable_out : out std_logic_vector(3 downto 0);
102  gt0_rxbyteisaligned_out : out std_logic;
103  gt0_rxbyterealign_out : out std_logic;
104  gt0_rxcommadet_out : out std_logic;
106  gt0_rxchariscomma_out : out std_logic_vector(3 downto 0);
107  gt0_rxcharisk_out : out std_logic_vector(3 downto 0);
109  gt0_rxresetdone_out : out std_logic;
110 
112  gt0_txdata_in : in std_logic_vector(31 downto 0);
114  gt0_txresetdone_out : out std_logic;
116  gt0_txcharisk_in : in std_logic_vector(3 downto 0);
118  gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
119 
120  --GT1 (X0Y1)
121  --____________________________CHANNEL PORTS________________________________
123  gt1_loopback_in : in std_logic_vector(2 downto 0);
125  gt1_rxpd_in : in std_logic_vector(1 downto 0);
126  gt1_txpd_in : in std_logic_vector(1 downto 0);
128  gt1_rxdata_out : out std_logic_vector(31 downto 0);
130  gt1_rxdisperr_out : out std_logic_vector(3 downto 0);
131  gt1_rxnotintable_out : out std_logic_vector(3 downto 0);
133  gt1_rxbyteisaligned_out : out std_logic;
134  gt1_rxbyterealign_out : out std_logic;
135  gt1_rxcommadet_out : out std_logic;
137  gt1_rxchariscomma_out : out std_logic_vector(3 downto 0);
138  gt1_rxcharisk_out : out std_logic_vector(3 downto 0);
140  gt1_rxresetdone_out : out std_logic;
142  gt1_txdata_in : in std_logic_vector(31 downto 0);
144  gt1_txresetdone_out : out std_logic;
146  gt1_txcharisk_in : in std_logic_vector(3 downto 0);
148  gt1_txbufstatus_out : out std_logic_vector(1 downto 0);
149 
150  --GT2 (X0Y2)
151  --____________________________CHANNEL PORTS________________________________
153  gt2_loopback_in : in std_logic_vector(2 downto 0);
155  gt2_rxpd_in : in std_logic_vector(1 downto 0);
156  gt2_txpd_in : in std_logic_vector(1 downto 0);
158  gt2_rxdata_out : out std_logic_vector(31 downto 0);
160  gt2_rxdisperr_out : out std_logic_vector(3 downto 0);
161  gt2_rxnotintable_out : out std_logic_vector(3 downto 0);
163  gt2_rxbyteisaligned_out : out std_logic;
164  gt2_rxbyterealign_out : out std_logic;
165  gt2_rxcommadet_out : out std_logic;
167  gt2_rxchariscomma_out : out std_logic_vector(3 downto 0);
168  gt2_rxcharisk_out : out std_logic_vector(3 downto 0);
170  gt2_rxresetdone_out : out std_logic;
172  gt2_txdata_in : in std_logic_vector(31 downto 0);
174  gt2_txresetdone_out : out std_logic;
176  gt2_txcharisk_in : in std_logic_vector(3 downto 0);
178  gt2_txbufstatus_out : out std_logic_vector(1 downto 0);
179 
180  --GT3 (X0Y3)
181  --____________________________CHANNEL PORTS________________________________
182  ---! Loopback Ports for gt3
183  gt3_loopback_in : in std_logic_vector(2 downto 0);
185  gt3_rxpd_in : in std_logic_vector(1 downto 0);
186  gt3_txpd_in : in std_logic_vector(1 downto 0);
188  gt3_rxdata_out : out std_logic_vector(31 downto 0);
190  gt3_rxdisperr_out : out std_logic_vector(3 downto 0);
191  gt3_rxnotintable_out : out std_logic_vector(3 downto 0);
193  gt3_rxbyteisaligned_out : out std_logic;
194  gt3_rxbyterealign_out : out std_logic;
195  gt3_rxcommadet_out : out std_logic;
197  gt3_rxchariscomma_out : out std_logic_vector(3 downto 0);
198  gt3_rxcharisk_out : out std_logic_vector(3 downto 0);
200  gt3_rxresetdone_out : out std_logic;
202  gt3_txdata_in : in std_logic_vector(31 downto 0);
204  gt3_txresetdone_out : out std_logic;
206  gt3_txcharisk_in : in std_logic_vector(3 downto 0);
208  gt3_txbufstatus_out : out std_logic_vector(1 downto 0);
209 
210  --____________________________COMMON PORTS________________________________
211  -- GT0_QPLLLOCK_OUT : out std_logic;
212  --GT0_QPLLREFCLKLOST_OUT : out std_logic;
213  sysclk_in : in std_logic
214 
215  );
216 
217 
218 end mgt_tx_rx_6g4_wrapper;
219 
221 architecture RTL of mgt_tx_rx_6g4_wrapper is
222 
223 
224  attribute DowngradeIPIdentifiedWarnings: string;
225  attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
226 
227  attribute CORE_GENERATION_INFO : string;
228  attribute CORE_GENERATION_INFO of RTL : architecture is "MGT_TX_RX_6G4,gtwizard_v3_6_5,{protocol_file=Start_from_scratch}";
229 
230 --**************************Component Declarations*****************************
231 
232 
233 
234  signal tied_to_ground_i : std_logic;
235  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
236  signal tied_to_vcc_i : std_logic;
237  signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
238 
239 
240  signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
241  signal gt0_drpdi_i : std_logic_vector(15 downto 0);
242  signal gt0_drpdo_i : std_logic_vector(15 downto 0);
243  signal gt0_drpen_i : std_logic;
244  signal gt0_drprdy_i : std_logic;
245  signal gt0_drpwe_i : std_logic;
246  signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
247  signal gt1_drpdi_i : std_logic_vector(15 downto 0);
248  signal gt1_drpdo_i : std_logic_vector(15 downto 0);
249  signal gt1_drpen_i : std_logic;
250  signal gt1_drprdy_i : std_logic;
251  signal gt1_drpwe_i : std_logic;
252  signal gt2_drpaddr_i : std_logic_vector(8 downto 0);
253  signal gt2_drpdi_i : std_logic_vector(15 downto 0);
254  signal gt2_drpdo_i : std_logic_vector(15 downto 0);
255  signal gt2_drpen_i : std_logic;
256  signal gt2_drprdy_i : std_logic;
257  signal gt2_drpwe_i : std_logic;
258  signal gt3_drpaddr_i : std_logic_vector(8 downto 0);
259  signal gt3_drpdi_i : std_logic_vector(15 downto 0);
260  signal gt3_drpdo_i : std_logic_vector(15 downto 0);
261  signal gt3_drpen_i : std_logic;
262  signal gt3_drprdy_i : std_logic;
263  signal gt3_drpwe_i : std_logic;
264 
265 
266 
267 
268 
269 --**************************** Main Body of Code *******************************
270 
271 begin
272 
273  -- Static signal Assigments
274  tied_to_ground_i <= '0';
275  tied_to_ground_vec_i <= x"0000000000000000";
276  tied_to_vcc_i <= '1';
277  tied_to_vcc_vec_i <= "11111111";
278 
279 
280  ----------------------------- The GT Wrapper -----------------------------
281 
282  -- Use the instantiation template in the example directory to add the GT wrapper to your design.
283  -- In this example, the wrapper is wired up for basic operation with a frame generator and frame
284  -- checker. The GTs will reset, then attempt to align and transmit data. If channel bonding is
285  -- enabled, bonding should occur after alignment.
286 
287 
288  min_latency_1_quad_rx_tx_support_i : entity work.MGT_TX_RX_6G4_support
289  generic map
290  (
291  EXAMPLE_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
292  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD
293  )
294  port map
295  ( --refclk160 => refclk160 ,
296  SOFT_RESET_TX_IN => SOFT_RESET_TX_IN,
297  SOFT_RESET_RX_IN => SOFT_RESET_RX_IN,
298  DONT_RESET_ON_DATA_ERROR_IN => tied_to_ground_i,
299  Q1_CLK0_GTREFCLK_PAD_N_IN => Q0_CLK0_GTREFCLK_PAD_N_IN,
300  Q1_CLK0_GTREFCLK_PAD_P_IN => Q0_CLK0_GTREFCLK_PAD_P_IN,
301 
302  GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
303  GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
304  GT0_DATA_VALID_IN => '1' ,
305  GT1_TX_FSM_RESET_DONE_OUT => GT1_TX_FSM_RESET_DONE_OUT,
306  GT1_RX_FSM_RESET_DONE_OUT => GT1_RX_FSM_RESET_DONE_OUT,
307  GT1_DATA_VALID_IN => '1' ,
308  GT2_TX_FSM_RESET_DONE_OUT => GT2_TX_FSM_RESET_DONE_OUT,
309  GT2_RX_FSM_RESET_DONE_OUT => GT2_RX_FSM_RESET_DONE_OUT,
310  GT2_DATA_VALID_IN => '1' ,
311  GT3_TX_FSM_RESET_DONE_OUT => GT3_TX_FSM_RESET_DONE_OUT,
312  GT3_RX_FSM_RESET_DONE_OUT => GT3_RX_FSM_RESET_DONE_OUT,
313  GT3_DATA_VALID_IN => '1' ,
314  GT0_TXUSRCLK_OUT => GT0_TXUSRCLK_OUT ,
315  GT0_TXUSRCLK2_OUT => open ,
316  GT0_RXUSRCLK_OUT => GT0_RXUSRCLK_OUT ,
317  GT0_RXUSRCLK2_OUT => open ,
318  GT1_TXUSRCLK_OUT => GT1_TXUSRCLK_OUT ,
319  GT1_TXUSRCLK2_OUT => open ,
320  GT1_RXUSRCLK_OUT => GT1_RXUSRCLK_OUT ,
321  GT1_RXUSRCLK2_OUT => open ,
322  GT2_TXUSRCLK_OUT => GT2_TXUSRCLK_OUT ,
323  GT2_TXUSRCLK2_OUT => open ,
324  GT2_RXUSRCLK_OUT => GT2_RXUSRCLK_OUT ,
325  GT2_RXUSRCLK2_OUT => open ,
326  GT3_TXUSRCLK_OUT => GT3_TXUSRCLK_OUT ,
327  GT3_TXUSRCLK2_OUT => open ,
328  GT3_RXUSRCLK_OUT => GT3_RXUSRCLK_OUT ,
329  GT3_RXUSRCLK2_OUT => open ,
330 
331 
332  --_____________________________________________________________________
333  --_____________________________________________________________________
334  --GT0 (X0Y0)
335 
336  gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
337  gt0_cplllock_out => gt0_cplllock_out,
338  gt0_cpllreset_in => soft_reset_rx_in ,-- tied_to_ground_i,
339  ---------------------------- Channel - DRP Ports --------------------------
340  gt0_drpaddr_in => gt0_drpaddr_i,
341  gt0_drpdi_in => gt0_drpdi_i,
342  gt0_drpdo_out => gt0_drpdo_i,
343  gt0_drpen_in => gt0_drpen_i,
344  gt0_drprdy_out => gt0_drprdy_i,
345  gt0_drpwe_in => gt0_drpwe_i,
346  ------------------------------- Loopback Ports -----------------------------
347  gt0_loopback_in => gt0_loopback_in,
348  ------------------------------ Power-Down Ports ----------------------------
349  gt0_rxpd_in => gt0_rxpd_in,
350  gt0_txpd_in => gt0_txpd_in,
351  --------------------- RX Initialization and Reset Ports --------------------
352  gt0_eyescanreset_in => tied_to_ground_i,
353  gt0_rxuserrdy_in => tied_to_ground_i,
354  -------------------------- RX Margin Analysis Ports ------------------------
355  gt0_eyescandataerror_out => open,
356  gt0_eyescantrigger_in => tied_to_ground_i,
357  ------------------- Receive Ports - Digital Monitor Ports ------------------
358  gt0_dmonitorout_out => open,
359  ------------------ Receive Ports - FPGA RX interface Ports -----------------
360  gt0_rxdata_out => gt0_rxdata_out,
361  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
362  gt0_rxdisperr_out => gt0_rxdisperr_out,
363  gt0_rxnotintable_out => gt0_rxnotintable_out,
364  ------------------------ Receive Ports - RX AFE Ports ----------------------
365  gt0_gthrxn_in => RXN_IN(0),
366  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
367  gt0_rxphmonitor_out => open,
368  gt0_rxphslipmonitor_out => open,
369  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
370  gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
371  gt0_rxbyterealign_out => gt0_rxbyterealign_out,
372  gt0_rxcommadet_out => gt0_rxcommadet_out,
373  --------------------- Receive Ports - RX Equalizer Ports -------------------
374  gt0_rxmonitorout_out => open,
375  gt0_rxmonitorsel_in => "00",
376  --------------- Receive Ports - RX Fabric Output Control Ports -------------
377  gt0_rxoutclkfabric_out => open,
378  ------------- Receive Ports - RX Initialization and Reset Ports ------------
379  gt0_gtrxreset_in => tied_to_ground_i,
380  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
381  gt0_rxchariscomma_out => gt0_rxchariscomma_out,
382  gt0_rxcharisk_out => gt0_rxcharisk_out,
383  ------------------------ Receive Ports -RX AFE Ports -----------------------
384  gt0_gthrxp_in => RXP_IN(0),
385  -------------- Receive Ports -RX Initialization and Reset Ports ------------
386  gt0_rxresetdone_out => gt0_rxresetdone_out,
387  --------------------- TX Initialization and Reset Ports --------------------
388  gt0_gttxreset_in => tied_to_ground_i,
389  gt0_txuserrdy_in => tied_to_ground_i,
390  ---------------------- Transmit Ports - TX Buffer Ports --------------------
391  gt0_txbufstatus_out => gt0_txbufstatus_out,
392  ------------------ Transmit Ports - TX Data Path interface -----------------
393  gt0_txdata_in => gt0_txdata_in,
394  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
395  gt0_gthtxn_out => TXN_OUT(0),
396  gt0_gthtxp_out => TXP_OUT(0),
397  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
398  gt0_txoutclkfabric_out => open,
399  gt0_txoutclkpcs_out => open,
400  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
401  gt0_txresetdone_out => gt0_txresetdone_out,
402  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
403  gt0_txcharisk_in => gt0_txcharisk_in,
404 
405  --
406  ----------------------------------- CPLL Ports -------------------------------
407  gt1_cpllfbclklost_out => gt1_cpllfbclklost_out,
408  gt1_cplllock_out => gt1_cplllock_out,
409  gt1_cpllreset_in => soft_reset_rx_in , -- tied_to_ground_i,
410  ---------------------------- Channel - DRP Ports --------------------------
411  gt1_drpaddr_in => gt1_drpaddr_i,
412  gt1_drpdi_in => gt1_drpdi_i,
413  gt1_drpdo_out => gt1_drpdo_i,
414  gt1_drpen_in => gt1_drpen_i,
415  gt1_drprdy_out => gt1_drprdy_i,
416  gt1_drpwe_in => gt1_drpwe_i,
417  --_____________________________________________________________________
418  --_____________________________________________________________________
419  --GT1 (X0Y1)
420 
421  ------------------------------- Loopback Ports -----------------------------
422  gt1_loopback_in => gt1_loopback_in,
423  ------------------------------ Power-Down Ports ----------------------------
424  gt1_rxpd_in => gt1_rxpd_in,
425  gt1_txpd_in => gt1_txpd_in,
426  --------------------- RX Initialization and Reset Ports --------------------
427  gt1_eyescanreset_in => tied_to_ground_i,
428  gt1_rxuserrdy_in => tied_to_ground_i,
429  -------------------------- RX Margin Analysis Ports ------------------------
430  gt1_eyescandataerror_out => open,
431  gt1_eyescantrigger_in => tied_to_ground_i,
432  ------------------- Receive Ports - Digital Monitor Ports ------------------
433  gt1_dmonitorout_out => open,
434  ------------------ Receive Ports - FPGA RX interface Ports -----------------
435  gt1_rxdata_out => gt1_rxdata_out,
436  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
437  gt1_rxdisperr_out => gt1_rxdisperr_out,
438  gt1_rxnotintable_out => gt1_rxnotintable_out,
439  ------------------------ Receive Ports - RX AFE Ports ----------------------
440  gt1_gthrxn_in => RXN_IN(1),
441  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
442  gt1_rxphmonitor_out => open,
443  gt1_rxphslipmonitor_out => open,
444  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
445  gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
446  gt1_rxbyterealign_out => gt1_rxbyterealign_out,
447  gt1_rxcommadet_out => gt1_rxcommadet_out,
448  --------------------- Receive Ports - RX Equalizer Ports -------------------
449  gt1_rxmonitorout_out => open,
450  gt1_rxmonitorsel_in => "00",
451  --------------- Receive Ports - RX Fabric Output Control Ports -------------
452  gt1_rxoutclkfabric_out => open,
453  ------------- Receive Ports - RX Initialization and Reset Ports ------------
454  gt1_gtrxreset_in => tied_to_ground_i,
455  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
456  gt1_rxchariscomma_out => gt1_rxchariscomma_out,
457  gt1_rxcharisk_out => gt1_rxcharisk_out ,
458  ------------------------ Receive Ports -RX AFE Ports -----------------------
459  gt1_gthrxp_in => RXP_IN(1),
460  -------------- Receive Ports -RX Initialization and Reset Ports ------------
461  gt1_rxresetdone_out => gt1_rxresetdone_out,
462  --------------------- TX Initialization and Reset Ports --------------------
463  gt1_gttxreset_in => tied_to_ground_i,
464  gt1_txuserrdy_in => tied_to_ground_i,
465  ---------------------- Transmit Ports - TX Buffer Ports --------------------
466  gt1_txbufstatus_out => gt1_txbufstatus_out,
467  ------------------ Transmit Ports - TX Data Path interface -----------------
468  gt1_txdata_in => gt1_txdata_in,
469  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
470  gt1_gthtxn_out => TXN_OUT(1),
471  gt1_gthtxp_out => TXP_OUT(1),
472  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
473  gt1_txoutclkfabric_out => open,
474  gt1_txoutclkpcs_out => open,
475  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
476  gt1_txresetdone_out => gt1_txresetdone_out,
477  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
478  gt1_txcharisk_in => gt1_txcharisk_in,
479 
480  --_____________________________________________________________________
481  --_____________________________________________________________________
482  --GT2 (X0Y2)
483 
484  gt2_cpllfbclklost_out => gt2_cpllfbclklost_out,
485  gt2_cplllock_out => gt2_cplllock_out,
486  gt2_cpllreset_in => soft_reset_rx_in, -- tied_to_ground_i,
487  --------------------------- Channel - DRP Ports ------------
488  gt2_drpaddr_in => gt2_drpaddr_i,
489  gt2_drpdi_in => gt2_drpdi_i,
490  gt2_drpdo_out => gt2_drpdo_i,
491  gt2_drpen_in => gt2_drpen_i,
492  gt2_drprdy_out => gt2_drprdy_i,
493  gt2_drpwe_in => gt2_drpwe_i,
494 
495  ------------------------------- Loopback Ports -----------------------------
496  gt2_loopback_in => gt2_loopback_in,
497  ------------------------------ Power-Down Ports ----------------------------
498  gt2_rxpd_in => gt2_rxpd_in,
499  gt2_txpd_in => gt2_txpd_in,
500  -------------------- RX Initialization and Reset Ports --------------------
501  gt2_eyescanreset_in => tied_to_ground_i,
502  gt2_rxuserrdy_in => tied_to_ground_i,
503  -------------------------- RX Margin Analysis Ports ------------------------
504  gt2_eyescandataerror_out => open,
505  gt2_eyescantrigger_in => tied_to_ground_i,
506  ------------------- Receive Ports - Digital Monitor Ports ------------------
507  gt2_dmonitorout_out => open,
508  ------------------ Receive Ports - FPGA RX interface Ports -----------------
509  gt2_rxdata_out => gt2_rxdata_out,
510  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
511  gt2_rxdisperr_out => gt2_rxdisperr_out,
512  gt2_rxnotintable_out => gt2_rxnotintable_out,
513  ------------------------ Receive Ports - RX AFE Ports ----------------------
514  gt2_gthrxn_in => RXN_IN(2),
515  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
516  gt2_rxphmonitor_out => open,
517  gt2_rxphslipmonitor_out => open,
518  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
519  gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
520  gt2_rxbyterealign_out => gt2_rxbyterealign_out ,
521  gt2_rxcommadet_out => gt2_rxcommadet_out ,
522  --------------------- Receive Ports - RX Equalizer Ports -------------------
523  gt2_rxmonitorout_out => open,
524  gt2_rxmonitorsel_in => "00",
525  --------------- Receive Ports - RX Fabric Output Control Ports -------------
526  gt2_rxoutclkfabric_out => open,
527  ------------- Receive Ports - RX Initialization and Reset Ports ------------
528  gt2_gtrxreset_in => tied_to_ground_i,
529  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
530  gt2_rxchariscomma_out => gt2_rxchariscomma_out,
531  gt2_rxcharisk_out => gt2_rxcharisk_out ,
532  ------------------------ Receive Ports -RX AFE Ports -----------------------
533  gt2_gthrxp_in => RXP_IN(2),
534  -------------- Receive Ports -RX Initialization and Reset Ports ------------
535  gt2_rxresetdone_out => gt2_rxresetdone_out,
536  --------------------- TX Initialization and Reset Ports --------------------
537  gt2_gttxreset_in => tied_to_ground_i,
538  gt2_txuserrdy_in => tied_to_ground_i,
539  ---------------------- Transmit Ports - TX Buffer Ports --------------------
540  gt2_txbufstatus_out => gt2_txbufstatus_out,
541  ------------------ Transmit Ports - TX Data Path interface -----------------
542  gt2_txdata_in => gt2_txdata_in,
543  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
544  gt2_gthtxn_out => TXN_OUT(2),
545  gt2_gthtxp_out => TXP_OUT(2),
546  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
547  gt2_txoutclkfabric_out => open,
548  gt2_txoutclkpcs_out => open,
549  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
550  gt2_txresetdone_out => gt2_txresetdone_out,
551  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
552  gt2_txcharisk_in => gt2_txcharisk_in,
553 
554  --_____________________________________________________________________
555  --_____________________________________________________________________
556  --GT3 (X0Y3)
557 
558  gt3_cpllfbclklost_out => gt3_cpllfbclklost_out,
559  gt3_cplllock_out => gt3_cplllock_out,
560  gt3_cpllreset_in => soft_reset_rx_in , -- tied_to_ground_i,
561  ---------------------------- Channel - DRP Ports ------------
562  gt3_drpaddr_in => gt3_drpaddr_i,
563  gt3_drpdi_in => gt3_drpdi_i,
564  gt3_drpdo_out => gt3_drpdo_i,
565  gt3_drpen_in => gt3_drpen_i,
566  gt3_drprdy_out => gt3_drprdy_i,
567  gt3_drpwe_in => gt3_drpwe_i,
568  ------------------------------- Loopback Ports -----------------------------
569  gt3_loopback_in => gt3_loopback_in,
570  ------------------------------ Power-Down Ports ----------------------------
571  gt3_rxpd_in => gt3_rxpd_in,
572  gt3_txpd_in => gt3_txpd_in,
573 
574  --------------------- RX Initialization and Reset Ports --------------------
575  gt3_eyescanreset_in => tied_to_ground_i,
576  gt3_rxuserrdy_in => tied_to_ground_i,
577  -------------------------- RX Margin Analysis Ports ------------------------
578  gt3_eyescandataerror_out => open,
579  gt3_eyescantrigger_in => tied_to_ground_i,
580  ------------------- Receive Ports - Digital Monitor Ports ------------------
581  gt3_dmonitorout_out => open,
582  ------------------ Receive Ports - FPGA RX interface Ports -----------------
583  gt3_rxdata_out => gt3_rxdata_out,
584  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
585  gt3_rxdisperr_out => gt3_rxdisperr_out ,
586  gt3_rxnotintable_out => gt3_rxnotintable_out,
587  ------------------------ Receive Ports - RX AFE Ports ----------------------
588  gt3_gthrxn_in => RXN_IN(3),
589  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
590  gt3_rxphmonitor_out => open,
591  gt3_rxphslipmonitor_out => open,
592  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
593  gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
594  gt3_rxbyterealign_out => gt3_rxbyterealign_out ,
595  gt3_rxcommadet_out => gt3_rxcommadet_out ,
596  --------------------- Receive Ports - RX Equalizer Ports -------------------
597  gt3_rxmonitorout_out => open,
598  gt3_rxmonitorsel_in => "00",
599  --------------- Receive Ports - RX Fabric Output Control Ports -------------
600  gt3_rxoutclkfabric_out => open,
601  ------------- Receive Ports - RX Initialization and Reset Ports ------------
602  gt3_gtrxreset_in => tied_to_ground_i,
603  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
604  gt3_rxchariscomma_out => gt3_rxchariscomma_out,
605  gt3_rxcharisk_out => gt3_rxcharisk_out ,
606  ------------------------ Receive Ports -RX AFE Ports -----------------------
607  gt3_gthrxp_in => RXP_IN(3),
608  -------------- Receive Ports -RX Initialization and Reset Ports ------------
609  gt3_rxresetdone_out => gt3_rxresetdone_out,
610  --------------------- TX Initialization and Reset Ports --------------------
611  gt3_gttxreset_in => tied_to_ground_i,
612  gt3_txuserrdy_in => tied_to_ground_i,
613  ---------------------- Transmit Ports - TX Buffer Ports --------------------
614  gt3_txbufstatus_out => gt3_txbufstatus_out,
615  ------------------ Transmit Ports - TX Data Path interface -----------------
616  gt3_txdata_in => gt3_txdata_in,
617  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
618  gt3_gthtxn_out => TXN_OUT(3),
619  gt3_gthtxp_out => TXP_OUT(3),
620  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
621  gt3_txoutclkfabric_out => open,
622  gt3_txoutclkpcs_out => open,
623  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
624  gt3_txresetdone_out => gt3_txresetdone_out,
625  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
626  gt3_txcharisk_in => gt3_txcharisk_in,
627 
628  --____________________________COMMON PORTS________________________________
629 
630  GT0_QPLLOUTCLK_OUT => open,
631  GT0_QPLLOUTREFCLK_OUT => open,
632  sysclk_in => sysclk_in
633  );
634 
635  gt0_drpaddr_i <= (others => '0');
636  gt0_drpdi_i <= (others => '0');
637  gt0_drpen_i <= '0';
638  gt0_drpwe_i <= '0';
639  gt1_drpaddr_i <= (others => '0');
640  gt1_drpdi_i <= (others => '0');
641  gt1_drpen_i <= '0';
642  gt1_drpwe_i <= '0';
643  gt2_drpaddr_i <= (others => '0');
644  gt2_drpdi_i <= (others => '0');
645  gt2_drpen_i <= '0';
646  gt2_drpwe_i <= '0';
647  gt3_drpaddr_i <= (others => '0');
648  gt3_drpdi_i <= (others => '0');
649  gt3_drpen_i <= '0';
650  gt3_drpwe_i <= '0';
651 
652 end RTL;
653 
MGT_TX_RX_6G4_support
Definition: mgt_tx_rx_6g4_support.vhd:74
mgt_tx_rx_6g4_wrapper.RTL
mgt selection wrapper
Definition: mgt_tx_rx_6g4_wrapper.vhd:221
mgt_tx_rx_6g4_wrapper
mgt selection wrapper
Definition: mgt_tx_rx_6g4_wrapper.vhd:17
mgt_tx_rx_6g4_wrapper.gt1_rxdata_out
out gt1_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:128
mgt_tx_rx_6g4_wrapper.gt3_txbufstatus_out
out gt3_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:208
mgt_tx_rx_6g4_wrapper.gt3_rxbyteisaligned_out
out gt3_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:193
mgt_tx_rx_6g4_wrapper.gt2_txresetdone_out
out gt2_txresetdone_out std_logic
Transmit Ports - TX Fabric Clock Output Control Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:174
mgt_tx_rx_6g4_wrapper.gt1_txdata_in
in gt1_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:142
mgt_tx_rx_6g4_wrapper.GT0_TXUSRCLK_OUT
out GT0_TXUSRCLK_OUT std_logic
tx user clock out gt0
Definition: mgt_tx_rx_6g4_wrapper.vhd:56
mgt_tx_rx_6g4_wrapper.gt0_txbufstatus_out
out gt0_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:118
mgt_tx_rx_6g4_wrapper.TXN_OUT
out TXN_OUT std_logic_vector( 3 downto 0)
tx quad output
Definition: mgt_tx_rx_6g4_wrapper.vhd:34
mgt_tx_rx_6g4_wrapper.gt0_rxdisperr_out
out gt0_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:99
mgt_tx_rx_6g4_wrapper.GT3_TX_FSM_RESET_DONE_OUT
out GT3_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:52
mgt_tx_rx_6g4_wrapper.GT2_RX_FSM_RESET_DONE_OUT
out GT2_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:50
mgt_tx_rx_6g4_wrapper.gt2_rxresetdone_out
out gt2_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:170
mgt_tx_rx_6g4_wrapper.gt2_cplllock_out
out gt2_cplllock_out std_logic
gt2_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:82
mgt_tx_rx_6g4_wrapper.gt2_rxpd_in
in gt2_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:155
mgt_tx_rx_6g4_wrapper.gt1_txbufstatus_out
out gt1_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:148
mgt_tx_rx_6g4_wrapper.gt0_rxdata_out
out gt0_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:97
mgt_tx_rx_6g4_wrapper.GT2_TXUSRCLK_OUT
out GT2_TXUSRCLK_OUT std_logic
tx user clock out gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:64
mgt_tx_rx_6g4_wrapper.gt3_rxdisperr_out
out gt3_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:190
mgt_tx_rx_6g4_wrapper.gt2_loopback_in
in gt2_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:153
mgt_tx_rx_6g4_wrapper.gt2_cpllfbclklost_out
out gt2_cpllfbclklost_out std_logic
gt2_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:80
mgt_tx_rx_6g4_wrapper.gt1_rxresetdone_out
out gt1_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:140
mgt_tx_rx_6g4_wrapper.gt1_cpllfbclklost_out
out gt1_cpllfbclklost_out std_logic
gt1_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:76
mgt_tx_rx_6g4_wrapper.gt0_txdata_in
in gt0_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:112
mgt_tx_rx_6g4_wrapper.gt3_rxdata_out
out gt3_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:188
mgt_tx_rx_6g4_wrapper.gt2_rxbyteisaligned_out
out gt2_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:163
mgt_tx_rx_6g4_wrapper.gt0_cplllock_out
out gt0_cplllock_out std_logic
gt0_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:74
mgt_tx_rx_6g4_wrapper.GT1_RX_FSM_RESET_DONE_OUT
out GT1_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:46
mgt_tx_rx_6g4_wrapper.gt0_rxchariscomma_out
out gt0_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:106
mgt_tx_rx_6g4_wrapper.gt0_txresetdone_out
out gt0_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:114
mgt_tx_rx_6g4_wrapper.GT3_TXUSRCLK_OUT
out GT3_TXUSRCLK_OUT std_logic
tx user clock out gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:68
mgt_tx_rx_6g4_wrapper.GT3_RX_FSM_RESET_DONE_OUT
out GT3_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:54
mgt_tx_rx_6g4_wrapper.gt2_rxdisperr_out
out gt2_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:160
mgt_tx_rx_6g4_wrapper.gt0_rxresetdone_out
out gt0_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:109
mgt_tx_rx_6g4_wrapper.gt3_txdata_in
in gt3_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:202
mgt_tx_rx_6g4_wrapper.gt3_rxresetdone_out
out gt3_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:200
mgt_tx_rx_6g4_wrapper.gt2_txbufstatus_out
out gt2_txbufstatus_out std_logic_vector( 1 downto 0)
Transmit Ports - TX Buffer Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:178
mgt_tx_rx_6g4_wrapper.gt3_txcharisk_in
in gt3_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:206
mgt_tx_rx_6g4_wrapper.gt0_rxpd_in
in gt0_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:94
mgt_tx_rx_6g4_wrapper.gt2_rxchariscomma_out
out gt2_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:167
mgt_tx_rx_6g4_wrapper.GT3_RXUSRCLK_OUT
out GT3_RXUSRCLK_OUT std_logic
rx user clock out gt3
Definition: mgt_tx_rx_6g4_wrapper.vhd:70
mgt_tx_rx_6g4_wrapper.gt0_rxbyteisaligned_out
out gt0_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:102
mgt_tx_rx_6g4_wrapper.GT0_TX_FSM_RESET_DONE_OUT
out GT0_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt0
Definition: mgt_tx_rx_6g4_wrapper.vhd:40
mgt_tx_rx_6g4_wrapper.SOFT_RESET_TX_IN
in SOFT_RESET_TX_IN std_logic
soft reset of tx quad
Definition: mgt_tx_rx_6g4_wrapper.vhd:27
mgt_tx_rx_6g4_wrapper.GT1_RXUSRCLK_OUT
out GT1_RXUSRCLK_OUT std_logic
rx user clock out gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:62
mgt_tx_rx_6g4_wrapper.gt1_txresetdone_out
out gt1_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:144
mgt_tx_rx_6g4_wrapper.gt1_txcharisk_in
in gt1_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:146
mgt_tx_rx_6g4_wrapper.gt1_rxpd_in
in gt1_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:125
mgt_tx_rx_6g4_wrapper.gt1_rxbyteisaligned_out
out gt1_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:133
mgt_tx_rx_6g4_wrapper.RXN_IN
in RXN_IN std_logic_vector( 3 downto 0)
rx quad input
Definition: mgt_tx_rx_6g4_wrapper.vhd:31
mgt_tx_rx_6g4_wrapper.GT2_RXUSRCLK_OUT
out GT2_RXUSRCLK_OUT std_logic
rx user clock out gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:66
mgt_tx_rx_6g4_wrapper.gt1_rxchariscomma_out
out gt1_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:137
mgt_tx_rx_6g4_wrapper.gt2_rxdata_out
out gt2_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:158
mgt_tx_rx_6g4_wrapper.gt3_rxpd_in
in gt3_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:185
mgt_tx_rx_6g4_wrapper.Q0_CLK0_GTREFCLK_PAD_N_IN
in Q0_CLK0_GTREFCLK_PAD_N_IN std_logic
clock input to the quad
Definition: mgt_tx_rx_6g4_wrapper.vhd:37
mgt_tx_rx_6g4_wrapper.gt2_txcharisk_in
in gt2_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:176
mgt_tx_rx_6g4_wrapper.gt3_rxchariscomma_out
out gt3_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:197
mgt_tx_rx_6g4_wrapper.gt0_cpllfbclklost_out
out gt0_cpllfbclklost_out std_logic
gt0_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:72
mgt_tx_rx_6g4_wrapper.gt2_txdata_in
in gt2_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt2.
Definition: mgt_tx_rx_6g4_wrapper.vhd:172
mgt_tx_rx_6g4_wrapper.GT2_TX_FSM_RESET_DONE_OUT
out GT2_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt2
Definition: mgt_tx_rx_6g4_wrapper.vhd:48
mgt_tx_rx_6g4_wrapper.gt1_loopback_in
in gt1_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:123
mgt_tx_rx_6g4_wrapper.gt3_cpllfbclklost_out
out gt3_cpllfbclklost_out std_logic
gt3_cpllfbclklost_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:84
mgt_tx_rx_6g4_wrapper.gt1_cplllock_out
out gt1_cplllock_out std_logic
gt1_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:78
mgt_tx_rx_6g4_wrapper.gt0_txcharisk_in
in gt0_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:116
mgt_tx_rx_6g4_wrapper.GT0_RXUSRCLK_OUT
out GT0_RXUSRCLK_OUT std_logic
rx user clock out gt0
Definition: mgt_tx_rx_6g4_wrapper.vhd:58
mgt_tx_rx_6g4_wrapper.GT0_RX_FSM_RESET_DONE_OUT
out GT0_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gto
Definition: mgt_tx_rx_6g4_wrapper.vhd:42
mgt_tx_rx_6g4_wrapper.gt1_rxdisperr_out
out gt1_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt1.
Definition: mgt_tx_rx_6g4_wrapper.vhd:130
mgt_tx_rx_6g4_wrapper.gt3_txresetdone_out
out gt3_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt3.
Definition: mgt_tx_rx_6g4_wrapper.vhd:204
mgt_tx_rx_6g4_wrapper.SOFT_RESET_RX_IN
in SOFT_RESET_RX_IN std_logic
soft reset of rx quad
Definition: mgt_tx_rx_6g4_wrapper.vhd:29
mgt_tx_rx_6g4_wrapper.gt0_loopback_in
in gt0_loopback_in std_logic_vector( 2 downto 0)
Loopback Ports for gt0.
Definition: mgt_tx_rx_6g4_wrapper.vhd:92
mgt_tx_rx_6g4_wrapper.gt3_cplllock_out
out gt3_cplllock_out std_logic
gt3_cplllock_out
Definition: mgt_tx_rx_6g4_wrapper.vhd:86
mgt_tx_rx_6g4_wrapper.GT1_TX_FSM_RESET_DONE_OUT
out GT1_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:44
mgt_tx_rx_6g4_wrapper.GT1_TXUSRCLK_OUT
out GT1_TXUSRCLK_OUT std_logic
tx user clock out gt1
Definition: mgt_tx_rx_6g4_wrapper.vhd:60
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