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ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt_tx_rx_6g4_support.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : mgt_tx_rx_6g4_support.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module MGT_TX_RX_6G4_support
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
21 -- This file contains confidential and proprietary information
22 -- of Xilinx, Inc. and is protected under U.S. and
23 -- international copyright and other intellectual property
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25 --
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 --***********************************Entity Declaration************************
73 
74 entity MGT_TX_RX_6G4_support is
75 generic
76 (
77  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
78  STABLE_CLOCK_PERIOD : integer := 16
79 
80 );
81 port
82 (
83  SOFT_RESET_TX_IN : in std_logic;
84  SOFT_RESET_RX_IN : in std_logic;
85  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
86  Q1_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
87  Q1_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
88 
89  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_DATA_VALID_IN : in std_logic;
92  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
93  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
94  GT1_DATA_VALID_IN : in std_logic;
95  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
96  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
97  GT2_DATA_VALID_IN : in std_logic;
98  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
99  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
100  GT3_DATA_VALID_IN : in std_logic;
101 
102  GT0_TXUSRCLK_OUT : out std_logic;
103  GT0_TXUSRCLK2_OUT : out std_logic;
104  GT0_RXUSRCLK_OUT : out std_logic;
105  GT0_RXUSRCLK2_OUT : out std_logic;
106 
107  GT1_TXUSRCLK_OUT : out std_logic;
108  GT1_TXUSRCLK2_OUT : out std_logic;
109  GT1_RXUSRCLK_OUT : out std_logic;
110  GT1_RXUSRCLK2_OUT : out std_logic;
111 
112  GT2_TXUSRCLK_OUT : out std_logic;
113  GT2_TXUSRCLK2_OUT : out std_logic;
114  GT2_RXUSRCLK_OUT : out std_logic;
115  GT2_RXUSRCLK2_OUT : out std_logic;
116 
117  GT3_TXUSRCLK_OUT : out std_logic;
118  GT3_TXUSRCLK2_OUT : out std_logic;
119  GT3_RXUSRCLK_OUT : out std_logic;
120  GT3_RXUSRCLK2_OUT : out std_logic;
121 
122  --_________________________________________________________________________
123  --GT0 (X1Y4)
124  --____________________________CHANNEL PORTS________________________________
125  --------------------------------- CPLL Ports -------------------------------
126  gt0_cpllfbclklost_out : out std_logic;
127  gt0_cplllock_out : out std_logic;
128  gt0_cpllreset_in : in std_logic;
129  ---------------------------- Channel - DRP Ports --------------------------
130  gt0_drpaddr_in : in std_logic_vector(8 downto 0);
131  gt0_drpdi_in : in std_logic_vector(15 downto 0);
132  gt0_drpdo_out : out std_logic_vector(15 downto 0);
133  gt0_drpen_in : in std_logic;
134  gt0_drprdy_out : out std_logic;
135  gt0_drpwe_in : in std_logic;
136  ------------------------------- Loopback Ports -----------------------------
137  gt0_loopback_in : in std_logic_vector(2 downto 0);
138  ------------------------------ Power-Down Ports ----------------------------
139  gt0_rxpd_in : in std_logic_vector(1 downto 0);
140  gt0_txpd_in : in std_logic_vector(1 downto 0);
141  --------------------- RX Initialization and Reset Ports --------------------
142  gt0_eyescanreset_in : in std_logic;
143  gt0_rxuserrdy_in : in std_logic;
144  -------------------------- RX Margin Analysis Ports ------------------------
145  gt0_eyescandataerror_out : out std_logic;
146  gt0_eyescantrigger_in : in std_logic;
147  ------------------- Receive Ports - Digital Monitor Ports ------------------
148  gt0_dmonitorout_out : out std_logic_vector(14 downto 0);
149  ------------------ Receive Ports - FPGA RX interface Ports -----------------
150  gt0_rxdata_out : out std_logic_vector(31 downto 0);
151  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
152  gt0_rxdisperr_out : out std_logic_vector(3 downto 0);
153  gt0_rxnotintable_out : out std_logic_vector(3 downto 0);
154  ------------------------ Receive Ports - RX AFE Ports ----------------------
155  gt0_gthrxn_in : in std_logic;
156  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
157  gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
158  gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
159  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
160  gt0_rxbyteisaligned_out : out std_logic;
161  gt0_rxbyterealign_out : out std_logic;
162  gt0_rxcommadet_out : out std_logic;
163  --------------------- Receive Ports - RX Equalizer Ports -------------------
164  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
165  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
166  --------------- Receive Ports - RX Fabric Output Control Ports -------------
167  gt0_rxoutclkfabric_out : out std_logic;
168  ------------- Receive Ports - RX Initialization and Reset Ports ------------
169  gt0_gtrxreset_in : in std_logic;
170  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
171  gt0_rxchariscomma_out : out std_logic_vector(3 downto 0);
172  gt0_rxcharisk_out : out std_logic_vector(3 downto 0);
173  ------------------------ Receive Ports -RX AFE Ports -----------------------
174  gt0_gthrxp_in : in std_logic;
175  -------------- Receive Ports -RX Initialization and Reset Ports ------------
176  gt0_rxresetdone_out : out std_logic;
177  --------------------- TX Initialization and Reset Ports --------------------
178  gt0_gttxreset_in : in std_logic;
179  gt0_txuserrdy_in : in std_logic;
180  ---------------------- Transmit Ports - TX Buffer Ports --------------------
181  gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
182  ------------------ Transmit Ports - TX Data Path interface -----------------
183  gt0_txdata_in : in std_logic_vector(31 downto 0);
184  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
185  gt0_gthtxn_out : out std_logic;
186  gt0_gthtxp_out : out std_logic;
187  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
188  gt0_txoutclkfabric_out : out std_logic;
189  gt0_txoutclkpcs_out : out std_logic;
190  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
191  gt0_txresetdone_out : out std_logic;
192  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
193  gt0_txcharisk_in : in std_logic_vector(3 downto 0);
194 
195  --GT1 (X1Y5)
196  --____________________________CHANNEL PORTS________________________________
197  --------------------------------- CPLL Ports -------------------------------
198  gt1_cpllfbclklost_out : out std_logic;
199  gt1_cplllock_out : out std_logic;
200  gt1_cpllreset_in : in std_logic;
201  ---------------------------- Channel - DRP Ports --------------------------
202  gt1_drpaddr_in : in std_logic_vector(8 downto 0);
203  gt1_drpdi_in : in std_logic_vector(15 downto 0);
204  gt1_drpdo_out : out std_logic_vector(15 downto 0);
205  gt1_drpen_in : in std_logic;
206  gt1_drprdy_out : out std_logic;
207  gt1_drpwe_in : in std_logic;
208  ------------------------------- Loopback Ports -----------------------------
209  gt1_loopback_in : in std_logic_vector(2 downto 0);
210  ------------------------------ Power-Down Ports ----------------------------
211  gt1_rxpd_in : in std_logic_vector(1 downto 0);
212  gt1_txpd_in : in std_logic_vector(1 downto 0);
213  --------------------- RX Initialization and Reset Ports --------------------
214  gt1_eyescanreset_in : in std_logic;
215  gt1_rxuserrdy_in : in std_logic;
216  -------------------------- RX Margin Analysis Ports ------------------------
217  gt1_eyescandataerror_out : out std_logic;
218  gt1_eyescantrigger_in : in std_logic;
219  ------------------- Receive Ports - Digital Monitor Ports ------------------
220  gt1_dmonitorout_out : out std_logic_vector(14 downto 0);
221  ------------------ Receive Ports - FPGA RX interface Ports -----------------
222  gt1_rxdata_out : out std_logic_vector(31 downto 0);
223  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
224  gt1_rxdisperr_out : out std_logic_vector(3 downto 0);
225  gt1_rxnotintable_out : out std_logic_vector(3 downto 0);
226  ------------------------ Receive Ports - RX AFE Ports ----------------------
227  gt1_gthrxn_in : in std_logic;
228  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
229  gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
230  gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
231  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
232  gt1_rxbyteisaligned_out : out std_logic;
233  gt1_rxbyterealign_out : out std_logic;
234  gt1_rxcommadet_out : out std_logic;
235  --------------------- Receive Ports - RX Equalizer Ports -------------------
236  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
237  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
238  --------------- Receive Ports - RX Fabric Output Control Ports -------------
239  gt1_rxoutclkfabric_out : out std_logic;
240  ------------- Receive Ports - RX Initialization and Reset Ports ------------
241  gt1_gtrxreset_in : in std_logic;
242  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
243  gt1_rxchariscomma_out : out std_logic_vector(3 downto 0);
244  gt1_rxcharisk_out : out std_logic_vector(3 downto 0);
245  ------------------------ Receive Ports -RX AFE Ports -----------------------
246  gt1_gthrxp_in : in std_logic;
247  -------------- Receive Ports -RX Initialization and Reset Ports ------------
248  gt1_rxresetdone_out : out std_logic;
249  --------------------- TX Initialization and Reset Ports --------------------
250  gt1_gttxreset_in : in std_logic;
251  gt1_txuserrdy_in : in std_logic;
252  ---------------------- Transmit Ports - TX Buffer Ports --------------------
253  gt1_txbufstatus_out : out std_logic_vector(1 downto 0);
254  ------------------ Transmit Ports - TX Data Path interface -----------------
255  gt1_txdata_in : in std_logic_vector(31 downto 0);
256  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
257  gt1_gthtxn_out : out std_logic;
258  gt1_gthtxp_out : out std_logic;
259  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
260  gt1_txoutclkfabric_out : out std_logic;
261  gt1_txoutclkpcs_out : out std_logic;
262  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
263  gt1_txresetdone_out : out std_logic;
264  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
265  gt1_txcharisk_in : in std_logic_vector(3 downto 0);
266 
267  --GT2 (X1Y6)
268  --____________________________CHANNEL PORTS________________________________
269  --------------------------------- CPLL Ports -------------------------------
270  gt2_cpllfbclklost_out : out std_logic;
271  gt2_cplllock_out : out std_logic;
272  gt2_cpllreset_in : in std_logic;
273  ---------------------------- Channel - DRP Ports --------------------------
274  gt2_drpaddr_in : in std_logic_vector(8 downto 0);
275  gt2_drpdi_in : in std_logic_vector(15 downto 0);
276  gt2_drpdo_out : out std_logic_vector(15 downto 0);
277  gt2_drpen_in : in std_logic;
278  gt2_drprdy_out : out std_logic;
279  gt2_drpwe_in : in std_logic;
280  ------------------------------- Loopback Ports -----------------------------
281  gt2_loopback_in : in std_logic_vector(2 downto 0);
282  ------------------------------ Power-Down Ports ----------------------------
283  gt2_rxpd_in : in std_logic_vector(1 downto 0);
284  gt2_txpd_in : in std_logic_vector(1 downto 0);
285  --------------------- RX Initialization and Reset Ports --------------------
286  gt2_eyescanreset_in : in std_logic;
287  gt2_rxuserrdy_in : in std_logic;
288  -------------------------- RX Margin Analysis Ports ------------------------
289  gt2_eyescandataerror_out : out std_logic;
290  gt2_eyescantrigger_in : in std_logic;
291  ------------------- Receive Ports - Digital Monitor Ports ------------------
292  gt2_dmonitorout_out : out std_logic_vector(14 downto 0);
293  ------------------ Receive Ports - FPGA RX interface Ports -----------------
294  gt2_rxdata_out : out std_logic_vector(31 downto 0);
295  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
296  gt2_rxdisperr_out : out std_logic_vector(3 downto 0);
297  gt2_rxnotintable_out : out std_logic_vector(3 downto 0);
298  ------------------------ Receive Ports - RX AFE Ports ----------------------
299  gt2_gthrxn_in : in std_logic;
300  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
301  gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
302  gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
303  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
304  gt2_rxbyteisaligned_out : out std_logic;
305  gt2_rxbyterealign_out : out std_logic;
306  gt2_rxcommadet_out : out std_logic;
307  --------------------- Receive Ports - RX Equalizer Ports -------------------
308  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
309  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
310  --------------- Receive Ports - RX Fabric Output Control Ports -------------
311  gt2_rxoutclkfabric_out : out std_logic;
312  ------------- Receive Ports - RX Initialization and Reset Ports ------------
313  gt2_gtrxreset_in : in std_logic;
314  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
315  gt2_rxchariscomma_out : out std_logic_vector(3 downto 0);
316  gt2_rxcharisk_out : out std_logic_vector(3 downto 0);
317  ------------------------ Receive Ports -RX AFE Ports -----------------------
318  gt2_gthrxp_in : in std_logic;
319  -------------- Receive Ports -RX Initialization and Reset Ports ------------
320  gt2_rxresetdone_out : out std_logic;
321  --------------------- TX Initialization and Reset Ports --------------------
322  gt2_gttxreset_in : in std_logic;
323  gt2_txuserrdy_in : in std_logic;
324  ---------------------- Transmit Ports - TX Buffer Ports --------------------
325  gt2_txbufstatus_out : out std_logic_vector(1 downto 0);
326  ------------------ Transmit Ports - TX Data Path interface -----------------
327  gt2_txdata_in : in std_logic_vector(31 downto 0);
328  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
329  gt2_gthtxn_out : out std_logic;
330  gt2_gthtxp_out : out std_logic;
331  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
332  gt2_txoutclkfabric_out : out std_logic;
333  gt2_txoutclkpcs_out : out std_logic;
334  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
335  gt2_txresetdone_out : out std_logic;
336  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
337  gt2_txcharisk_in : in std_logic_vector(3 downto 0);
338 
339  --GT3 (X1Y7)
340  --____________________________CHANNEL PORTS________________________________
341  --------------------------------- CPLL Ports -------------------------------
342  gt3_cpllfbclklost_out : out std_logic;
343  gt3_cplllock_out : out std_logic;
344  gt3_cpllreset_in : in std_logic;
345  ---------------------------- Channel - DRP Ports --------------------------
346  gt3_drpaddr_in : in std_logic_vector(8 downto 0);
347  gt3_drpdi_in : in std_logic_vector(15 downto 0);
348  gt3_drpdo_out : out std_logic_vector(15 downto 0);
349  gt3_drpen_in : in std_logic;
350  gt3_drprdy_out : out std_logic;
351  gt3_drpwe_in : in std_logic;
352  ------------------------------- Loopback Ports -----------------------------
353  gt3_loopback_in : in std_logic_vector(2 downto 0);
354  ------------------------------ Power-Down Ports ----------------------------
355  gt3_rxpd_in : in std_logic_vector(1 downto 0);
356  gt3_txpd_in : in std_logic_vector(1 downto 0);
357  --------------------- RX Initialization and Reset Ports --------------------
358  gt3_eyescanreset_in : in std_logic;
359  gt3_rxuserrdy_in : in std_logic;
360  -------------------------- RX Margin Analysis Ports ------------------------
361  gt3_eyescandataerror_out : out std_logic;
362  gt3_eyescantrigger_in : in std_logic;
363  ------------------- Receive Ports - Digital Monitor Ports ------------------
364  gt3_dmonitorout_out : out std_logic_vector(14 downto 0);
365  ------------------ Receive Ports - FPGA RX interface Ports -----------------
366  gt3_rxdata_out : out std_logic_vector(31 downto 0);
367  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
368  gt3_rxdisperr_out : out std_logic_vector(3 downto 0);
369  gt3_rxnotintable_out : out std_logic_vector(3 downto 0);
370  ------------------------ Receive Ports - RX AFE Ports ----------------------
371  gt3_gthrxn_in : in std_logic;
372  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
373  gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
374  gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
375  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
376  gt3_rxbyteisaligned_out : out std_logic;
377  gt3_rxbyterealign_out : out std_logic;
378  gt3_rxcommadet_out : out std_logic;
379  --------------------- Receive Ports - RX Equalizer Ports -------------------
380  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
381  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
382  --------------- Receive Ports - RX Fabric Output Control Ports -------------
383  gt3_rxoutclkfabric_out : out std_logic;
384  ------------- Receive Ports - RX Initialization and Reset Ports ------------
385  gt3_gtrxreset_in : in std_logic;
386  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
387  gt3_rxchariscomma_out : out std_logic_vector(3 downto 0);
388  gt3_rxcharisk_out : out std_logic_vector(3 downto 0);
389  ------------------------ Receive Ports -RX AFE Ports -----------------------
390  gt3_gthrxp_in : in std_logic;
391  -------------- Receive Ports -RX Initialization and Reset Ports ------------
392  gt3_rxresetdone_out : out std_logic;
393  --------------------- TX Initialization and Reset Ports --------------------
394  gt3_gttxreset_in : in std_logic;
395  gt3_txuserrdy_in : in std_logic;
396  ---------------------- Transmit Ports - TX Buffer Ports --------------------
397  gt3_txbufstatus_out : out std_logic_vector(1 downto 0);
398  ------------------ Transmit Ports - TX Data Path interface -----------------
399  gt3_txdata_in : in std_logic_vector(31 downto 0);
400  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
401  gt3_gthtxn_out : out std_logic;
402  gt3_gthtxp_out : out std_logic;
403  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
404  gt3_txoutclkfabric_out : out std_logic;
405  gt3_txoutclkpcs_out : out std_logic;
406  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
407  gt3_txresetdone_out : out std_logic;
408  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
409  gt3_txcharisk_in : in std_logic_vector(3 downto 0);
410 
411  --____________________________COMMON PORTS________________________________
412  GT0_QPLLOUTCLK_OUT : out std_logic;
413  GT0_QPLLOUTREFCLK_OUT : out std_logic;
414  sysclk_in : in std_logic
415 
416 );
417 
418 end MGT_TX_RX_6G4_support;
419 
420 architecture RTL of MGT_TX_RX_6G4_support is
421 attribute DowngradeIPIdentifiedWarnings: string;
422 attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
423 
424 --**************************Component Declarations*****************************
425 
426 component MGT_TX_RX_6G4
427 
428 port
429 (
430  SYSCLK_IN : in std_logic;
431  SOFT_RESET_TX_IN : in std_logic;
432  SOFT_RESET_RX_IN : in std_logic;
433  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
434  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
435  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
436  GT0_DATA_VALID_IN : in std_logic;
437  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
438  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
439  GT1_DATA_VALID_IN : in std_logic;
440  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
441  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
442  GT2_DATA_VALID_IN : in std_logic;
443  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
444  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
445  GT3_DATA_VALID_IN : in std_logic;
446 
447  --_________________________________________________________________________
448  --GT0 (X1Y4)
449  --____________________________CHANNEL PORTS________________________________
450  --------------------------------- CPLL Ports -------------------------------
451  gt0_cpllfbclklost_out : out std_logic;
452  gt0_cplllock_out : out std_logic;
453  gt0_cplllockdetclk_in : in std_logic;
454  gt0_cpllreset_in : in std_logic;
455  -------------------------- Channel - Clocking Ports ------------------------
456  gt0_gtrefclk0_in : in std_logic;
457  gt0_gtrefclk1_in : in std_logic;
458  ---------------------------- Channel - DRP Ports --------------------------
459  gt0_drpaddr_in : in std_logic_vector(8 downto 0);
460  gt0_drpclk_in : in std_logic;
461  gt0_drpdi_in : in std_logic_vector(15 downto 0);
462  gt0_drpdo_out : out std_logic_vector(15 downto 0);
463  gt0_drpen_in : in std_logic;
464  gt0_drprdy_out : out std_logic;
465  gt0_drpwe_in : in std_logic;
466  ------------------------------- Loopback Ports -----------------------------
467  gt0_loopback_in : in std_logic_vector(2 downto 0);
468  ------------------------------ Power-Down Ports ----------------------------
469  gt0_rxpd_in : in std_logic_vector(1 downto 0);
470  gt0_txpd_in : in std_logic_vector(1 downto 0);
471  --------------------- RX Initialization and Reset Ports --------------------
472  gt0_eyescanreset_in : in std_logic;
473  gt0_rxuserrdy_in : in std_logic;
474  -------------------------- RX Margin Analysis Ports ------------------------
475  gt0_eyescandataerror_out : out std_logic;
476  gt0_eyescantrigger_in : in std_logic;
477  ------------------- Receive Ports - Digital Monitor Ports ------------------
478  gt0_dmonitorout_out : out std_logic_vector(14 downto 0);
479  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
480  gt0_rxusrclk_in : in std_logic;
481  gt0_rxusrclk2_in : in std_logic;
482  ------------------ Receive Ports - FPGA RX interface Ports -----------------
483  gt0_rxdata_out : out std_logic_vector(31 downto 0);
484  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
485  gt0_rxdisperr_out : out std_logic_vector(3 downto 0);
486  gt0_rxnotintable_out : out std_logic_vector(3 downto 0);
487  ------------------------ Receive Ports - RX AFE Ports ----------------------
488  gt0_gthrxn_in : in std_logic;
489  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
490  gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
491  gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
492  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
493  gt0_rxbyteisaligned_out : out std_logic;
494  gt0_rxbyterealign_out : out std_logic;
495  gt0_rxcommadet_out : out std_logic;
496  --------------------- Receive Ports - RX Equalizer Ports -------------------
497  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
498  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
499  --------------- Receive Ports - RX Fabric Output Control Ports -------------
500  gt0_rxoutclk_out : out std_logic;
501  gt0_rxoutclkfabric_out : out std_logic;
502  ------------- Receive Ports - RX Initialization and Reset Ports ------------
503  gt0_gtrxreset_in : in std_logic;
504  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
505  gt0_rxchariscomma_out : out std_logic_vector(3 downto 0);
506  gt0_rxcharisk_out : out std_logic_vector(3 downto 0);
507  ------------------------ Receive Ports -RX AFE Ports -----------------------
508  gt0_gthrxp_in : in std_logic;
509  -------------- Receive Ports -RX Initialization and Reset Ports ------------
510  gt0_rxresetdone_out : out std_logic;
511  --------------------- TX Initialization and Reset Ports --------------------
512  gt0_gttxreset_in : in std_logic;
513  gt0_txuserrdy_in : in std_logic;
514  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
515  gt0_txusrclk_in : in std_logic;
516  gt0_txusrclk2_in : in std_logic;
517  ---------------------- Transmit Ports - TX Buffer Ports --------------------
518  gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
519  ------------------ Transmit Ports - TX Data Path interface -----------------
520  gt0_txdata_in : in std_logic_vector(31 downto 0);
521  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
522  gt0_gthtxn_out : out std_logic;
523  gt0_gthtxp_out : out std_logic;
524  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
525  gt0_txoutclk_out : out std_logic;
526  gt0_txoutclkfabric_out : out std_logic;
527  gt0_txoutclkpcs_out : out std_logic;
528  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
529  gt0_txresetdone_out : out std_logic;
530  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
531  gt0_txcharisk_in : in std_logic_vector(3 downto 0);
532 
533  --GT1 (X1Y5)
534  --____________________________CHANNEL PORTS________________________________
535  --------------------------------- CPLL Ports -------------------------------
536  gt1_cpllfbclklost_out : out std_logic;
537  gt1_cplllock_out : out std_logic;
538  gt1_cplllockdetclk_in : in std_logic;
539  gt1_cpllreset_in : in std_logic;
540  -------------------------- Channel - Clocking Ports ------------------------
541  gt1_gtrefclk0_in : in std_logic;
542  gt1_gtrefclk1_in : in std_logic;
543  ---------------------------- Channel - DRP Ports --------------------------
544  gt1_drpaddr_in : in std_logic_vector(8 downto 0);
545  gt1_drpclk_in : in std_logic;
546  gt1_drpdi_in : in std_logic_vector(15 downto 0);
547  gt1_drpdo_out : out std_logic_vector(15 downto 0);
548  gt1_drpen_in : in std_logic;
549  gt1_drprdy_out : out std_logic;
550  gt1_drpwe_in : in std_logic;
551  ------------------------------- Loopback Ports -----------------------------
552  gt1_loopback_in : in std_logic_vector(2 downto 0);
553  ------------------------------ Power-Down Ports ----------------------------
554  gt1_rxpd_in : in std_logic_vector(1 downto 0);
555  gt1_txpd_in : in std_logic_vector(1 downto 0);
556  --------------------- RX Initialization and Reset Ports --------------------
557  gt1_eyescanreset_in : in std_logic;
558  gt1_rxuserrdy_in : in std_logic;
559  -------------------------- RX Margin Analysis Ports ------------------------
560  gt1_eyescandataerror_out : out std_logic;
561  gt1_eyescantrigger_in : in std_logic;
562  ------------------- Receive Ports - Digital Monitor Ports ------------------
563  gt1_dmonitorout_out : out std_logic_vector(14 downto 0);
564  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
565  gt1_rxusrclk_in : in std_logic;
566  gt1_rxusrclk2_in : in std_logic;
567  ------------------ Receive Ports - FPGA RX interface Ports -----------------
568  gt1_rxdata_out : out std_logic_vector(31 downto 0);
569  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
570  gt1_rxdisperr_out : out std_logic_vector(3 downto 0);
571  gt1_rxnotintable_out : out std_logic_vector(3 downto 0);
572  ------------------------ Receive Ports - RX AFE Ports ----------------------
573  gt1_gthrxn_in : in std_logic;
574  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
575  gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
576  gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
577  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
578  gt1_rxbyteisaligned_out : out std_logic;
579  gt1_rxbyterealign_out : out std_logic;
580  gt1_rxcommadet_out : out std_logic;
581  --------------------- Receive Ports - RX Equalizer Ports -------------------
582  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
583  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
584  --------------- Receive Ports - RX Fabric Output Control Ports -------------
585  gt1_rxoutclk_out : out std_logic;
586  gt1_rxoutclkfabric_out : out std_logic;
587  ------------- Receive Ports - RX Initialization and Reset Ports ------------
588  gt1_gtrxreset_in : in std_logic;
589  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
590  gt1_rxchariscomma_out : out std_logic_vector(3 downto 0);
591  gt1_rxcharisk_out : out std_logic_vector(3 downto 0);
592  ------------------------ Receive Ports -RX AFE Ports -----------------------
593  gt1_gthrxp_in : in std_logic;
594  -------------- Receive Ports -RX Initialization and Reset Ports ------------
595  gt1_rxresetdone_out : out std_logic;
596  --------------------- TX Initialization and Reset Ports --------------------
597  gt1_gttxreset_in : in std_logic;
598  gt1_txuserrdy_in : in std_logic;
599  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
600  gt1_txusrclk_in : in std_logic;
601  gt1_txusrclk2_in : in std_logic;
602  ---------------------- Transmit Ports - TX Buffer Ports --------------------
603  gt1_txbufstatus_out : out std_logic_vector(1 downto 0);
604  ------------------ Transmit Ports - TX Data Path interface -----------------
605  gt1_txdata_in : in std_logic_vector(31 downto 0);
606  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
607  gt1_gthtxn_out : out std_logic;
608  gt1_gthtxp_out : out std_logic;
609  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
610  gt1_txoutclk_out : out std_logic;
611  gt1_txoutclkfabric_out : out std_logic;
612  gt1_txoutclkpcs_out : out std_logic;
613  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
614  gt1_txresetdone_out : out std_logic;
615  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
616  gt1_txcharisk_in : in std_logic_vector(3 downto 0);
617 
618  --GT2 (X1Y6)
619  --____________________________CHANNEL PORTS________________________________
620  --------------------------------- CPLL Ports -------------------------------
621  gt2_cpllfbclklost_out : out std_logic;
622  gt2_cplllock_out : out std_logic;
623  gt2_cplllockdetclk_in : in std_logic;
624  gt2_cpllreset_in : in std_logic;
625  -------------------------- Channel - Clocking Ports ------------------------
626  gt2_gtrefclk0_in : in std_logic;
627  gt2_gtrefclk1_in : in std_logic;
628  ---------------------------- Channel - DRP Ports --------------------------
629  gt2_drpaddr_in : in std_logic_vector(8 downto 0);
630  gt2_drpclk_in : in std_logic;
631  gt2_drpdi_in : in std_logic_vector(15 downto 0);
632  gt2_drpdo_out : out std_logic_vector(15 downto 0);
633  gt2_drpen_in : in std_logic;
634  gt2_drprdy_out : out std_logic;
635  gt2_drpwe_in : in std_logic;
636  ------------------------------- Loopback Ports -----------------------------
637  gt2_loopback_in : in std_logic_vector(2 downto 0);
638  ------------------------------ Power-Down Ports ----------------------------
639  gt2_rxpd_in : in std_logic_vector(1 downto 0);
640  gt2_txpd_in : in std_logic_vector(1 downto 0);
641  --------------------- RX Initialization and Reset Ports --------------------
642  gt2_eyescanreset_in : in std_logic;
643  gt2_rxuserrdy_in : in std_logic;
644  -------------------------- RX Margin Analysis Ports ------------------------
645  gt2_eyescandataerror_out : out std_logic;
646  gt2_eyescantrigger_in : in std_logic;
647  ------------------- Receive Ports - Digital Monitor Ports ------------------
648  gt2_dmonitorout_out : out std_logic_vector(14 downto 0);
649  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
650  gt2_rxusrclk_in : in std_logic;
651  gt2_rxusrclk2_in : in std_logic;
652  ------------------ Receive Ports - FPGA RX interface Ports -----------------
653  gt2_rxdata_out : out std_logic_vector(31 downto 0);
654  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
655  gt2_rxdisperr_out : out std_logic_vector(3 downto 0);
656  gt2_rxnotintable_out : out std_logic_vector(3 downto 0);
657  ------------------------ Receive Ports - RX AFE Ports ----------------------
658  gt2_gthrxn_in : in std_logic;
659  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
660  gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
661  gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
662  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
663  gt2_rxbyteisaligned_out : out std_logic;
664  gt2_rxbyterealign_out : out std_logic;
665  gt2_rxcommadet_out : out std_logic;
666  --------------------- Receive Ports - RX Equalizer Ports -------------------
667  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
668  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
669  --------------- Receive Ports - RX Fabric Output Control Ports -------------
670  gt2_rxoutclk_out : out std_logic;
671  gt2_rxoutclkfabric_out : out std_logic;
672  ------------- Receive Ports - RX Initialization and Reset Ports ------------
673  gt2_gtrxreset_in : in std_logic;
674  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
675  gt2_rxchariscomma_out : out std_logic_vector(3 downto 0);
676  gt2_rxcharisk_out : out std_logic_vector(3 downto 0);
677  ------------------------ Receive Ports -RX AFE Ports -----------------------
678  gt2_gthrxp_in : in std_logic;
679  -------------- Receive Ports -RX Initialization and Reset Ports ------------
680  gt2_rxresetdone_out : out std_logic;
681  --------------------- TX Initialization and Reset Ports --------------------
682  gt2_gttxreset_in : in std_logic;
683  gt2_txuserrdy_in : in std_logic;
684  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
685  gt2_txusrclk_in : in std_logic;
686  gt2_txusrclk2_in : in std_logic;
687  ---------------------- Transmit Ports - TX Buffer Ports --------------------
688  gt2_txbufstatus_out : out std_logic_vector(1 downto 0);
689  ------------------ Transmit Ports - TX Data Path interface -----------------
690  gt2_txdata_in : in std_logic_vector(31 downto 0);
691  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
692  gt2_gthtxn_out : out std_logic;
693  gt2_gthtxp_out : out std_logic;
694  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
695  gt2_txoutclk_out : out std_logic;
696  gt2_txoutclkfabric_out : out std_logic;
697  gt2_txoutclkpcs_out : out std_logic;
698  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
699  gt2_txresetdone_out : out std_logic;
700  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
701  gt2_txcharisk_in : in std_logic_vector(3 downto 0);
702 
703  --GT3 (X1Y7)
704  --____________________________CHANNEL PORTS________________________________
705  --------------------------------- CPLL Ports -------------------------------
706  gt3_cpllfbclklost_out : out std_logic;
707  gt3_cplllock_out : out std_logic;
708  gt3_cplllockdetclk_in : in std_logic;
709  gt3_cpllreset_in : in std_logic;
710  -------------------------- Channel - Clocking Ports ------------------------
711  gt3_gtrefclk0_in : in std_logic;
712  gt3_gtrefclk1_in : in std_logic;
713  ---------------------------- Channel - DRP Ports --------------------------
714  gt3_drpaddr_in : in std_logic_vector(8 downto 0);
715  gt3_drpclk_in : in std_logic;
716  gt3_drpdi_in : in std_logic_vector(15 downto 0);
717  gt3_drpdo_out : out std_logic_vector(15 downto 0);
718  gt3_drpen_in : in std_logic;
719  gt3_drprdy_out : out std_logic;
720  gt3_drpwe_in : in std_logic;
721  ------------------------------- Loopback Ports -----------------------------
722  gt3_loopback_in : in std_logic_vector(2 downto 0);
723  ------------------------------ Power-Down Ports ----------------------------
724  gt3_rxpd_in : in std_logic_vector(1 downto 0);
725  gt3_txpd_in : in std_logic_vector(1 downto 0);
726  --------------------- RX Initialization and Reset Ports --------------------
727  gt3_eyescanreset_in : in std_logic;
728  gt3_rxuserrdy_in : in std_logic;
729  -------------------------- RX Margin Analysis Ports ------------------------
730  gt3_eyescandataerror_out : out std_logic;
731  gt3_eyescantrigger_in : in std_logic;
732  ------------------- Receive Ports - Digital Monitor Ports ------------------
733  gt3_dmonitorout_out : out std_logic_vector(14 downto 0);
734  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
735  gt3_rxusrclk_in : in std_logic;
736  gt3_rxusrclk2_in : in std_logic;
737  ------------------ Receive Ports - FPGA RX interface Ports -----------------
738  gt3_rxdata_out : out std_logic_vector(31 downto 0);
739  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
740  gt3_rxdisperr_out : out std_logic_vector(3 downto 0);
741  gt3_rxnotintable_out : out std_logic_vector(3 downto 0);
742  ------------------------ Receive Ports - RX AFE Ports ----------------------
743  gt3_gthrxn_in : in std_logic;
744  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
745  gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
746  gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
747  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
748  gt3_rxbyteisaligned_out : out std_logic;
749  gt3_rxbyterealign_out : out std_logic;
750  gt3_rxcommadet_out : out std_logic;
751  --------------------- Receive Ports - RX Equalizer Ports -------------------
752  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
753  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
754  --------------- Receive Ports - RX Fabric Output Control Ports -------------
755  gt3_rxoutclk_out : out std_logic;
756  gt3_rxoutclkfabric_out : out std_logic;
757  ------------- Receive Ports - RX Initialization and Reset Ports ------------
758  gt3_gtrxreset_in : in std_logic;
759  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
760  gt3_rxchariscomma_out : out std_logic_vector(3 downto 0);
761  gt3_rxcharisk_out : out std_logic_vector(3 downto 0);
762  ------------------------ Receive Ports -RX AFE Ports -----------------------
763  gt3_gthrxp_in : in std_logic;
764  -------------- Receive Ports -RX Initialization and Reset Ports ------------
765  gt3_rxresetdone_out : out std_logic;
766  --------------------- TX Initialization and Reset Ports --------------------
767  gt3_gttxreset_in : in std_logic;
768  gt3_txuserrdy_in : in std_logic;
769  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
770  gt3_txusrclk_in : in std_logic;
771  gt3_txusrclk2_in : in std_logic;
772  ---------------------- Transmit Ports - TX Buffer Ports --------------------
773  gt3_txbufstatus_out : out std_logic_vector(1 downto 0);
774  ------------------ Transmit Ports - TX Data Path interface -----------------
775  gt3_txdata_in : in std_logic_vector(31 downto 0);
776  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
777  gt3_gthtxn_out : out std_logic;
778  gt3_gthtxp_out : out std_logic;
779  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
780  gt3_txoutclk_out : out std_logic;
781  gt3_txoutclkfabric_out : out std_logic;
782  gt3_txoutclkpcs_out : out std_logic;
783  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
784  gt3_txresetdone_out : out std_logic;
785  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
786  gt3_txcharisk_in : in std_logic_vector(3 downto 0);
787 
788 
789  --____________________________COMMON PORTS________________________________
790  GT0_QPLLOUTCLK_IN : in std_logic;
791  GT0_QPLLOUTREFCLK_IN : in std_logic
792 
793 );
794 
795 end component;
796 
797 component MGT_TX_RX_6G4_common_reset
798 generic
799 (
800  STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
801  );
802 port
803  (
804  STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
805  SOFT_RESET : in std_logic; --User Reset, can be pulled any time
806  COMMON_RESET : out std_logic --Reset QPLL
807  );
808 end component;
809 
810 component MGT_TX_RX_6G4_common
811 generic
812 (
813  -- Simulation attributes
814  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
815  SIM_QPLLREFCLK_SEL :bit_vector := "001"
816 
817 );
818 port
819 (
820  QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
821  GTREFCLK0_IN : in std_logic;
822  GTREFCLK1_IN : in std_logic;
823  QPLLLOCK_OUT : out std_logic;
824  QPLLLOCKDETCLK_IN : in std_logic;
825  QPLLOUTCLK_OUT : out std_logic;
826  QPLLOUTREFCLK_OUT : out std_logic;
827  QPLLREFCLKLOST_OUT : out std_logic;
828  QPLLRESET_IN : in std_logic
829 
830 );
831 
832 end component;
833 
834 component MGT_TX_RX_6G4_GT_USRCLK_SOURCE
835 port
836 (
837 
838  GT0_TXUSRCLK_OUT : out std_logic;
839  GT0_TXUSRCLK2_OUT : out std_logic;
840  GT0_TXOUTCLK_IN : in std_logic;
841  GT0_RXUSRCLK_OUT : out std_logic;
842  GT0_RXUSRCLK2_OUT : out std_logic;
843  GT0_RXOUTCLK_IN : in std_logic;
844 
845  GT1_TXUSRCLK_OUT : out std_logic;
846  GT1_TXUSRCLK2_OUT : out std_logic;
847  GT1_TXOUTCLK_IN : in std_logic;
848  GT1_RXUSRCLK_OUT : out std_logic;
849  GT1_RXUSRCLK2_OUT : out std_logic;
850  GT1_RXOUTCLK_IN : in std_logic;
851 
852  GT2_TXUSRCLK_OUT : out std_logic;
853  GT2_TXUSRCLK2_OUT : out std_logic;
854  GT2_TXOUTCLK_IN : in std_logic;
855  GT2_RXUSRCLK_OUT : out std_logic;
856  GT2_RXUSRCLK2_OUT : out std_logic;
857  GT2_RXOUTCLK_IN : in std_logic;
858 
859  GT3_TXUSRCLK_OUT : out std_logic;
860  GT3_TXUSRCLK2_OUT : out std_logic;
861  GT3_TXOUTCLK_IN : in std_logic;
862  GT3_RXUSRCLK_OUT : out std_logic;
863  GT3_RXUSRCLK2_OUT : out std_logic;
864  GT3_RXOUTCLK_IN : in std_logic;
865  Q1_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
866  Q1_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
867  Q1_CLK0_GTREFCLK_OUT : out std_logic
868 );
869 end component;
870 
871 --***********************************Parameter Declarations********************
872 
873  constant DLY : time := 1 ns;
874 
875 --************************** Register Declarations ****************************
876 
877  signal gt0_txfsmresetdone_i : std_logic;
878 signal gt0_rxfsmresetdone_i : std_logic;
879  signal gt0_txfsmresetdone_r : std_logic;
880  signal gt0_txfsmresetdone_r2 : std_logic;
881 signal gt0_rxresetdone_r : std_logic;
882 signal gt0_rxresetdone_r2 : std_logic;
883 signal gt0_rxresetdone_r3 : std_logic;
884 
885 
886  signal gt1_txfsmresetdone_i : std_logic;
887 signal gt1_rxfsmresetdone_i : std_logic;
888  signal gt1_txfsmresetdone_r : std_logic;
889  signal gt1_txfsmresetdone_r2 : std_logic;
890 signal gt1_rxresetdone_r : std_logic;
891 signal gt1_rxresetdone_r2 : std_logic;
892 signal gt1_rxresetdone_r3 : std_logic;
893 
894 
895  signal gt2_txfsmresetdone_i : std_logic;
896 signal gt2_rxfsmresetdone_i : std_logic;
897  signal gt2_txfsmresetdone_r : std_logic;
898  signal gt2_txfsmresetdone_r2 : std_logic;
899 signal gt2_rxresetdone_r : std_logic;
900 signal gt2_rxresetdone_r2 : std_logic;
901 signal gt2_rxresetdone_r3 : std_logic;
902 
903 
904  signal gt3_txfsmresetdone_i : std_logic;
905 signal gt3_rxfsmresetdone_i : std_logic;
906  signal gt3_txfsmresetdone_r : std_logic;
907  signal gt3_txfsmresetdone_r2 : std_logic;
908 signal gt3_rxresetdone_r : std_logic;
909 signal gt3_rxresetdone_r2 : std_logic;
910 signal gt3_rxresetdone_r3 : std_logic;
911 
912 
913 signal reset_pulse : std_logic_vector(3 downto 0);
914  signal reset_counter : unsigned(5 downto 0) := "000000";
915 
916 --**************************** Wire Declarations ******************************
917  -------------------------- GT Wrapper Wires ------------------------------
918  --________________________________________________________________________
919  --________________________________________________________________________
920  --GT0 (X1Y4)
921 
922  --------------------------------- CPLL Ports -------------------------------
923  signal gt0_cpllfbclklost_i : std_logic;
924  signal gt0_cplllock_i : std_logic;
925  signal gt0_cpllrefclklost_i : std_logic;
926  signal gt0_cpllreset_i : std_logic;
927  ---------------------------- Channel - DRP Ports --------------------------
928  signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
929  signal gt0_drpdi_i : std_logic_vector(15 downto 0);
930  signal gt0_drpdo_i : std_logic_vector(15 downto 0);
931  signal gt0_drpen_i : std_logic;
932  signal gt0_drprdy_i : std_logic;
933  signal gt0_drpwe_i : std_logic;
934  ------------------------------- Loopback Ports -----------------------------
935  signal gt0_loopback_i : std_logic_vector(2 downto 0);
936  ------------------------------ Power-Down Ports ----------------------------
937  signal gt0_rxpd_i : std_logic_vector(1 downto 0);
938  signal gt0_txpd_i : std_logic_vector(1 downto 0);
939  --------------------- RX Initialization and Reset Ports --------------------
940  signal gt0_eyescanreset_i : std_logic;
941  signal gt0_rxuserrdy_i : std_logic;
942  -------------------------- RX Margin Analysis Ports ------------------------
943  signal gt0_eyescandataerror_i : std_logic;
944  signal gt0_eyescantrigger_i : std_logic;
945  ------------------- Receive Ports - Digital Monitor Ports ------------------
946  signal gt0_dmonitorout_i : std_logic_vector(14 downto 0);
947  ------------------ Receive Ports - FPGA RX interface Ports -----------------
948  signal gt0_rxdata_i : std_logic_vector(31 downto 0);
949  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
950  signal gt0_rxdisperr_i : std_logic_vector(3 downto 0);
951  signal gt0_rxnotintable_i : std_logic_vector(3 downto 0);
952  ------------------------ Receive Ports - RX AFE Ports ----------------------
953  signal gt0_gthrxn_i : std_logic;
954  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
955  signal gt0_rxdlyen_i : std_logic;
956  signal gt0_rxdlysreset_i : std_logic;
957  signal gt0_rxdlysresetdone_i : std_logic;
958  signal gt0_rxphalign_i : std_logic;
959  signal gt0_rxphaligndone_i : std_logic;
960  signal gt0_rxphalignen_i : std_logic;
961  signal gt0_rxphdlyreset_i : std_logic;
962  signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
963  signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
964  signal gt0_rxsyncallin_i : std_logic;
965  signal gt0_rxsyncdone_i : std_logic;
966  signal gt0_rxsyncin_i : std_logic;
967  signal gt0_rxsyncmode_i : std_logic;
968  signal gt0_rxsyncout_i : std_logic;
969  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
970  signal gt0_rxbyteisaligned_i : std_logic;
971  signal gt0_rxbyterealign_i : std_logic;
972  signal gt0_rxcommadet_i : std_logic;
973  --------------------- Receive Ports - RX Equalizer Ports -------------------
974  signal gt0_rxdfeagchold_i : std_logic;
975  signal gt0_rxdfelfhold_i : std_logic;
976  signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
977  signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
978  --------------- Receive Ports - RX Fabric Output Control Ports -------------
979  signal gt0_rxoutclk_i : std_logic;
980  signal gt0_rxoutclkfabric_i : std_logic;
981  ------------- Receive Ports - RX Initialization and Reset Ports ------------
982  signal gt0_gtrxreset_i : std_logic;
983  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
984  signal gt0_rxchariscomma_i : std_logic_vector(3 downto 0);
985  signal gt0_rxcharisk_i : std_logic_vector(3 downto 0);
986  ------------------------ Receive Ports -RX AFE Ports -----------------------
987  signal gt0_gthrxp_i : std_logic;
988  -------------- Receive Ports -RX Initialization and Reset Ports ------------
989  signal gt0_rxresetdone_i : std_logic;
990  --------------------- TX Initialization and Reset Ports --------------------
991  signal gt0_gttxreset_i : std_logic;
992  signal gt0_txuserrdy_i : std_logic;
993  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
994  signal gt0_txdlyen_i : std_logic;
995  signal gt0_txdlysreset_i : std_logic;
996  signal gt0_txdlysresetdone_i : std_logic;
997  signal gt0_txphalign_i : std_logic;
998  signal gt0_txphaligndone_i : std_logic;
999  signal gt0_txphalignen_i : std_logic;
1000  signal gt0_txphdlyreset_i : std_logic;
1001  signal gt0_txphinit_i : std_logic;
1002  signal gt0_txphinitdone_i : std_logic;
1003  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1004  signal gt0_txbufstatus_i : std_logic_vector(1 downto 0);
1005  ------------------ Transmit Ports - TX Data Path interface -----------------
1006  signal gt0_txdata_i : std_logic_vector(31 downto 0);
1007  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1008  signal gt0_gthtxn_i : std_logic;
1009  signal gt0_gthtxp_i : std_logic;
1010  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1011  signal gt0_txoutclk_i : std_logic;
1012  signal gt0_txoutclkfabric_i : std_logic;
1013  signal gt0_txoutclkpcs_i : std_logic;
1014  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1015  signal gt0_txresetdone_i : std_logic;
1016  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1017  signal gt0_txcharisk_i : std_logic_vector(3 downto 0);
1018 
1019  --________________________________________________________________________
1020  --________________________________________________________________________
1021  --GT1 (X1Y5)
1022 
1023  --------------------------------- CPLL Ports -------------------------------
1024  signal gt1_cpllfbclklost_i : std_logic;
1025  signal gt1_cplllock_i : std_logic;
1026  signal gt1_cpllrefclklost_i : std_logic;
1027  signal gt1_cpllreset_i : std_logic;
1028  ---------------------------- Channel - DRP Ports --------------------------
1029  signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
1030  signal gt1_drpdi_i : std_logic_vector(15 downto 0);
1031  signal gt1_drpdo_i : std_logic_vector(15 downto 0);
1032  signal gt1_drpen_i : std_logic;
1033  signal gt1_drprdy_i : std_logic;
1034  signal gt1_drpwe_i : std_logic;
1035  ------------------------------- Loopback Ports -----------------------------
1036  signal gt1_loopback_i : std_logic_vector(2 downto 0);
1037  ------------------------------ Power-Down Ports ----------------------------
1038  signal gt1_rxpd_i : std_logic_vector(1 downto 0);
1039  signal gt1_txpd_i : std_logic_vector(1 downto 0);
1040  --------------------- RX Initialization and Reset Ports --------------------
1041  signal gt1_eyescanreset_i : std_logic;
1042  signal gt1_rxuserrdy_i : std_logic;
1043  -------------------------- RX Margin Analysis Ports ------------------------
1044  signal gt1_eyescandataerror_i : std_logic;
1045  signal gt1_eyescantrigger_i : std_logic;
1046  ------------------- Receive Ports - Digital Monitor Ports ------------------
1047  signal gt1_dmonitorout_i : std_logic_vector(14 downto 0);
1048  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1049  signal gt1_rxdata_i : std_logic_vector(31 downto 0);
1050  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1051  signal gt1_rxdisperr_i : std_logic_vector(3 downto 0);
1052  signal gt1_rxnotintable_i : std_logic_vector(3 downto 0);
1053  ------------------------ Receive Ports - RX AFE Ports ----------------------
1054  signal gt1_gthrxn_i : std_logic;
1055  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1056  signal gt1_rxdlyen_i : std_logic;
1057  signal gt1_rxdlysreset_i : std_logic;
1058  signal gt1_rxdlysresetdone_i : std_logic;
1059  signal gt1_rxphalign_i : std_logic;
1060  signal gt1_rxphaligndone_i : std_logic;
1061  signal gt1_rxphalignen_i : std_logic;
1062  signal gt1_rxphdlyreset_i : std_logic;
1063  signal gt1_rxphmonitor_i : std_logic_vector(4 downto 0);
1064  signal gt1_rxphslipmonitor_i : std_logic_vector(4 downto 0);
1065  signal gt1_rxsyncallin_i : std_logic;
1066  signal gt1_rxsyncdone_i : std_logic;
1067  signal gt1_rxsyncin_i : std_logic;
1068  signal gt1_rxsyncmode_i : std_logic;
1069  signal gt1_rxsyncout_i : std_logic;
1070  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1071  signal gt1_rxbyteisaligned_i : std_logic;
1072  signal gt1_rxbyterealign_i : std_logic;
1073  signal gt1_rxcommadet_i : std_logic;
1074  --------------------- Receive Ports - RX Equalizer Ports -------------------
1075  signal gt1_rxdfeagchold_i : std_logic;
1076  signal gt1_rxdfelfhold_i : std_logic;
1077  signal gt1_rxmonitorout_i : std_logic_vector(6 downto 0);
1078  signal gt1_rxmonitorsel_i : std_logic_vector(1 downto 0);
1079  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1080  signal gt1_rxoutclk_i : std_logic;
1081  signal gt1_rxoutclkfabric_i : std_logic;
1082  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1083  signal gt1_gtrxreset_i : std_logic;
1084  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1085  signal gt1_rxchariscomma_i : std_logic_vector(3 downto 0);
1086  signal gt1_rxcharisk_i : std_logic_vector(3 downto 0);
1087  ------------------------ Receive Ports -RX AFE Ports -----------------------
1088  signal gt1_gthrxp_i : std_logic;
1089  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1090  signal gt1_rxresetdone_i : std_logic;
1091  --------------------- TX Initialization and Reset Ports --------------------
1092  signal gt1_gttxreset_i : std_logic;
1093  signal gt1_txuserrdy_i : std_logic;
1094  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
1095  signal gt1_txdlyen_i : std_logic;
1096  signal gt1_txdlysreset_i : std_logic;
1097  signal gt1_txdlysresetdone_i : std_logic;
1098  signal gt1_txphalign_i : std_logic;
1099  signal gt1_txphaligndone_i : std_logic;
1100  signal gt1_txphalignen_i : std_logic;
1101  signal gt1_txphdlyreset_i : std_logic;
1102  signal gt1_txphinit_i : std_logic;
1103  signal gt1_txphinitdone_i : std_logic;
1104  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1105  signal gt1_txbufstatus_i : std_logic_vector(1 downto 0);
1106  ------------------ Transmit Ports - TX Data Path interface -----------------
1107  signal gt1_txdata_i : std_logic_vector(31 downto 0);
1108  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1109  signal gt1_gthtxn_i : std_logic;
1110  signal gt1_gthtxp_i : std_logic;
1111  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1112  signal gt1_txoutclk_i : std_logic;
1113  signal gt1_txoutclkfabric_i : std_logic;
1114  signal gt1_txoutclkpcs_i : std_logic;
1115  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1116  signal gt1_txresetdone_i : std_logic;
1117  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1118  signal gt1_txcharisk_i : std_logic_vector(3 downto 0);
1119 
1120  --________________________________________________________________________
1121  --________________________________________________________________________
1122  --GT2 (X1Y6)
1123 
1124  --------------------------------- CPLL Ports -------------------------------
1125  signal gt2_cpllfbclklost_i : std_logic;
1126  signal gt2_cplllock_i : std_logic;
1127  signal gt2_cpllrefclklost_i : std_logic;
1128  signal gt2_cpllreset_i : std_logic;
1129  ---------------------------- Channel - DRP Ports --------------------------
1130  signal gt2_drpaddr_i : std_logic_vector(8 downto 0);
1131  signal gt2_drpdi_i : std_logic_vector(15 downto 0);
1132  signal gt2_drpdo_i : std_logic_vector(15 downto 0);
1133  signal gt2_drpen_i : std_logic;
1134  signal gt2_drprdy_i : std_logic;
1135  signal gt2_drpwe_i : std_logic;
1136  ------------------------------- Loopback Ports -----------------------------
1137  signal gt2_loopback_i : std_logic_vector(2 downto 0);
1138  ------------------------------ Power-Down Ports ----------------------------
1139  signal gt2_rxpd_i : std_logic_vector(1 downto 0);
1140  signal gt2_txpd_i : std_logic_vector(1 downto 0);
1141  --------------------- RX Initialization and Reset Ports --------------------
1142  signal gt2_eyescanreset_i : std_logic;
1143  signal gt2_rxuserrdy_i : std_logic;
1144  -------------------------- RX Margin Analysis Ports ------------------------
1145  signal gt2_eyescandataerror_i : std_logic;
1146  signal gt2_eyescantrigger_i : std_logic;
1147  ------------------- Receive Ports - Digital Monitor Ports ------------------
1148  signal gt2_dmonitorout_i : std_logic_vector(14 downto 0);
1149  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1150  signal gt2_rxdata_i : std_logic_vector(31 downto 0);
1151  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1152  signal gt2_rxdisperr_i : std_logic_vector(3 downto 0);
1153  signal gt2_rxnotintable_i : std_logic_vector(3 downto 0);
1154  ------------------------ Receive Ports - RX AFE Ports ----------------------
1155  signal gt2_gthrxn_i : std_logic;
1156  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1157  signal gt2_rxdlyen_i : std_logic;
1158  signal gt2_rxdlysreset_i : std_logic;
1159  signal gt2_rxdlysresetdone_i : std_logic;
1160  signal gt2_rxphalign_i : std_logic;
1161  signal gt2_rxphaligndone_i : std_logic;
1162  signal gt2_rxphalignen_i : std_logic;
1163  signal gt2_rxphdlyreset_i : std_logic;
1164  signal gt2_rxphmonitor_i : std_logic_vector(4 downto 0);
1165  signal gt2_rxphslipmonitor_i : std_logic_vector(4 downto 0);
1166  signal gt2_rxsyncallin_i : std_logic;
1167  signal gt2_rxsyncdone_i : std_logic;
1168  signal gt2_rxsyncin_i : std_logic;
1169  signal gt2_rxsyncmode_i : std_logic;
1170  signal gt2_rxsyncout_i : std_logic;
1171  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1172  signal gt2_rxbyteisaligned_i : std_logic;
1173  signal gt2_rxbyterealign_i : std_logic;
1174  signal gt2_rxcommadet_i : std_logic;
1175  --------------------- Receive Ports - RX Equalizer Ports -------------------
1176  signal gt2_rxdfeagchold_i : std_logic;
1177  signal gt2_rxdfelfhold_i : std_logic;
1178  signal gt2_rxmonitorout_i : std_logic_vector(6 downto 0);
1179  signal gt2_rxmonitorsel_i : std_logic_vector(1 downto 0);
1180  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1181  signal gt2_rxoutclk_i : std_logic;
1182  signal gt2_rxoutclkfabric_i : std_logic;
1183  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1184  signal gt2_gtrxreset_i : std_logic;
1185  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1186  signal gt2_rxchariscomma_i : std_logic_vector(3 downto 0);
1187  signal gt2_rxcharisk_i : std_logic_vector(3 downto 0);
1188  ------------------------ Receive Ports -RX AFE Ports -----------------------
1189  signal gt2_gthrxp_i : std_logic;
1190  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1191  signal gt2_rxresetdone_i : std_logic;
1192  --------------------- TX Initialization and Reset Ports --------------------
1193  signal gt2_gttxreset_i : std_logic;
1194  signal gt2_txuserrdy_i : std_logic;
1195  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
1196  signal gt2_txdlyen_i : std_logic;
1197  signal gt2_txdlysreset_i : std_logic;
1198  signal gt2_txdlysresetdone_i : std_logic;
1199  signal gt2_txphalign_i : std_logic;
1200  signal gt2_txphaligndone_i : std_logic;
1201  signal gt2_txphalignen_i : std_logic;
1202  signal gt2_txphdlyreset_i : std_logic;
1203  signal gt2_txphinit_i : std_logic;
1204  signal gt2_txphinitdone_i : std_logic;
1205  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1206  signal gt2_txbufstatus_i : std_logic_vector(1 downto 0);
1207  ------------------ Transmit Ports - TX Data Path interface -----------------
1208  signal gt2_txdata_i : std_logic_vector(31 downto 0);
1209  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1210  signal gt2_gthtxn_i : std_logic;
1211  signal gt2_gthtxp_i : std_logic;
1212  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1213  signal gt2_txoutclk_i : std_logic;
1214  signal gt2_txoutclkfabric_i : std_logic;
1215  signal gt2_txoutclkpcs_i : std_logic;
1216  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1217  signal gt2_txresetdone_i : std_logic;
1218  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1219  signal gt2_txcharisk_i : std_logic_vector(3 downto 0);
1220 
1221  --________________________________________________________________________
1222  --________________________________________________________________________
1223  --GT3 (X1Y7)
1224 
1225  --------------------------------- CPLL Ports -------------------------------
1226  signal gt3_cpllfbclklost_i : std_logic;
1227  signal gt3_cplllock_i : std_logic;
1228  signal gt3_cpllrefclklost_i : std_logic;
1229  signal gt3_cpllreset_i : std_logic;
1230  ---------------------------- Channel - DRP Ports --------------------------
1231  signal gt3_drpaddr_i : std_logic_vector(8 downto 0);
1232  signal gt3_drpdi_i : std_logic_vector(15 downto 0);
1233  signal gt3_drpdo_i : std_logic_vector(15 downto 0);
1234  signal gt3_drpen_i : std_logic;
1235  signal gt3_drprdy_i : std_logic;
1236  signal gt3_drpwe_i : std_logic;
1237  ------------------------------- Loopback Ports -----------------------------
1238  signal gt3_loopback_i : std_logic_vector(2 downto 0);
1239  ------------------------------ Power-Down Ports ----------------------------
1240  signal gt3_rxpd_i : std_logic_vector(1 downto 0);
1241  signal gt3_txpd_i : std_logic_vector(1 downto 0);
1242  --------------------- RX Initialization and Reset Ports --------------------
1243  signal gt3_eyescanreset_i : std_logic;
1244  signal gt3_rxuserrdy_i : std_logic;
1245  -------------------------- RX Margin Analysis Ports ------------------------
1246  signal gt3_eyescandataerror_i : std_logic;
1247  signal gt3_eyescantrigger_i : std_logic;
1248  ------------------- Receive Ports - Digital Monitor Ports ------------------
1249  signal gt3_dmonitorout_i : std_logic_vector(14 downto 0);
1250  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1251  signal gt3_rxdata_i : std_logic_vector(31 downto 0);
1252  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1253  signal gt3_rxdisperr_i : std_logic_vector(3 downto 0);
1254  signal gt3_rxnotintable_i : std_logic_vector(3 downto 0);
1255  ------------------------ Receive Ports - RX AFE Ports ----------------------
1256  signal gt3_gthrxn_i : std_logic;
1257  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1258  signal gt3_rxdlyen_i : std_logic;
1259  signal gt3_rxdlysreset_i : std_logic;
1260  signal gt3_rxdlysresetdone_i : std_logic;
1261  signal gt3_rxphalign_i : std_logic;
1262  signal gt3_rxphaligndone_i : std_logic;
1263  signal gt3_rxphalignen_i : std_logic;
1264  signal gt3_rxphdlyreset_i : std_logic;
1265  signal gt3_rxphmonitor_i : std_logic_vector(4 downto 0);
1266  signal gt3_rxphslipmonitor_i : std_logic_vector(4 downto 0);
1267  signal gt3_rxsyncallin_i : std_logic;
1268  signal gt3_rxsyncdone_i : std_logic;
1269  signal gt3_rxsyncin_i : std_logic;
1270  signal gt3_rxsyncmode_i : std_logic;
1271  signal gt3_rxsyncout_i : std_logic;
1272  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1273  signal gt3_rxbyteisaligned_i : std_logic;
1274  signal gt3_rxbyterealign_i : std_logic;
1275  signal gt3_rxcommadet_i : std_logic;
1276  --------------------- Receive Ports - RX Equalizer Ports -------------------
1277  signal gt3_rxdfeagchold_i : std_logic;
1278  signal gt3_rxdfelfhold_i : std_logic;
1279  signal gt3_rxmonitorout_i : std_logic_vector(6 downto 0);
1280  signal gt3_rxmonitorsel_i : std_logic_vector(1 downto 0);
1281  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1282  signal gt3_rxoutclk_i : std_logic;
1283  signal gt3_rxoutclkfabric_i : std_logic;
1284  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1285  signal gt3_gtrxreset_i : std_logic;
1286  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1287  signal gt3_rxchariscomma_i : std_logic_vector(3 downto 0);
1288  signal gt3_rxcharisk_i : std_logic_vector(3 downto 0);
1289  ------------------------ Receive Ports -RX AFE Ports -----------------------
1290  signal gt3_gthrxp_i : std_logic;
1291  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1292  signal gt3_rxresetdone_i : std_logic;
1293  --------------------- TX Initialization and Reset Ports --------------------
1294  signal gt3_gttxreset_i : std_logic;
1295  signal gt3_txuserrdy_i : std_logic;
1296  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
1297  signal gt3_txdlyen_i : std_logic;
1298  signal gt3_txdlysreset_i : std_logic;
1299  signal gt3_txdlysresetdone_i : std_logic;
1300  signal gt3_txphalign_i : std_logic;
1301  signal gt3_txphaligndone_i : std_logic;
1302  signal gt3_txphalignen_i : std_logic;
1303  signal gt3_txphdlyreset_i : std_logic;
1304  signal gt3_txphinit_i : std_logic;
1305  signal gt3_txphinitdone_i : std_logic;
1306  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1307  signal gt3_txbufstatus_i : std_logic_vector(1 downto 0);
1308  ------------------ Transmit Ports - TX Data Path interface -----------------
1309  signal gt3_txdata_i : std_logic_vector(31 downto 0);
1310  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1311  signal gt3_gthtxn_i : std_logic;
1312  signal gt3_gthtxp_i : std_logic;
1313  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1314  signal gt3_txoutclk_i : std_logic;
1315  signal gt3_txoutclkfabric_i : std_logic;
1316  signal gt3_txoutclkpcs_i : std_logic;
1317  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1318  signal gt3_txresetdone_i : std_logic;
1319  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1320  signal gt3_txcharisk_i : std_logic_vector(3 downto 0);
1321 
1322  --____________________________COMMON PORTS________________________________
1323  signal gt0_qplllock_i : std_logic;
1324  signal gt0_qpllrefclklost_i : std_logic;
1325  signal gt0_qpllreset_i : std_logic;
1326  signal gt0_qpllreset_t : std_logic;
1327  signal gt0_qplloutclk_i : std_logic;
1328  signal gt0_qplloutrefclk_i : std_logic;
1329 
1330  ------------------------------- Global Signals -----------------------------
1331  signal gt0_tx_system_reset_c : std_logic;
1332  signal gt0_rx_system_reset_c : std_logic;
1333  signal gt1_tx_system_reset_c : std_logic;
1334  signal gt1_rx_system_reset_c : std_logic;
1335  signal gt2_tx_system_reset_c : std_logic;
1336  signal gt2_rx_system_reset_c : std_logic;
1337  signal gt3_tx_system_reset_c : std_logic;
1338  signal gt3_rx_system_reset_c : std_logic;
1339  signal tied_to_ground_i : std_logic;
1340  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
1341  signal tied_to_vcc_i : std_logic;
1342  signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
1343  signal drpclk_in_i : std_logic;
1344  signal sysclk_in_i : std_logic;
1345  signal GTTXRESET_IN : std_logic;
1346  signal GTRXRESET_IN : std_logic;
1347  signal CPLLRESET_IN : std_logic;
1348  signal QPLLRESET_IN : std_logic;
1349 
1350  attribute keep: string;
1351  ------------------------------- User Clocks ---------------------------------
1352  signal gt0_txusrclk_i : std_logic;
1353  signal gt0_txusrclk2_i : std_logic;
1354  signal gt0_rxusrclk_i : std_logic;
1355  signal gt0_rxusrclk2_i : std_logic;
1356 
1357 
1358 
1359 
1360  signal gt1_txusrclk_i : std_logic;
1361  signal gt1_txusrclk2_i : std_logic;
1362  signal gt1_rxusrclk_i : std_logic;
1363  signal gt1_rxusrclk2_i : std_logic;
1364 
1365 
1366 
1367 
1368  signal gt2_txusrclk_i : std_logic;
1369  signal gt2_txusrclk2_i : std_logic;
1370  signal gt2_rxusrclk_i : std_logic;
1371  signal gt2_rxusrclk2_i : std_logic;
1372 
1373 
1374 
1375 
1376  signal gt3_txusrclk_i : std_logic;
1377  signal gt3_txusrclk2_i : std_logic;
1378  signal gt3_rxusrclk_i : std_logic;
1379  signal gt3_rxusrclk2_i : std_logic;
1380 
1381 
1382 
1383 
1384  ----------------------------- Reference Clocks ----------------------------
1385 
1386 signal q1_clk0_refclk_i : std_logic;
1387 
1388 signal commonreset_i : std_logic;
1389 --**************************** Main Body of Code *******************************
1390 begin
1391 
1392  -- Static signal Assigments
1393 tied_to_ground_i <= '0';
1394 tied_to_ground_vec_i <= x"0000000000000000";
1395 tied_to_vcc_i <= '1';
1396 tied_to_vcc_vec_i <= "11111111";
1397 
1398 
1399  gt0_qpllreset_t <= commonreset_i or gt0_qpllreset_i; --tied_to_vcc_i;
1400  gt0_qplloutclk_out <= gt0_qplloutclk_i;
1401  gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
1402 
1403 
1404 
1405  GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
1406  GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
1407  GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
1408  GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
1409 
1410  GT1_TXUSRCLK_OUT <= gt1_txusrclk_i;
1411  GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
1412  GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
1413  GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
1414 
1415  GT2_TXUSRCLK_OUT <= gt2_txusrclk_i;
1416  GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
1417  GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
1418  GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
1419 
1420  GT3_TXUSRCLK_OUT <= gt3_txusrclk_i;
1421  GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
1422  GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
1423  GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
1424 
1425 
1426 
1427 
1428 
1429 
1430 
1431 
1432 
1433 
1434  gt_usrclk_source : MGT_TX_RX_6G4_GT_USRCLK_SOURCE
1435  port map
1436  (
1437 
1438  GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
1439  GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
1440  GT0_TXOUTCLK_IN => gt0_txoutclk_i,
1441  GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
1442  GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
1443  GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
1444 
1445  GT1_TXUSRCLK_OUT => gt1_txusrclk_i,
1446  GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
1447  GT1_TXOUTCLK_IN => gt1_txoutclk_i,
1448  GT1_RXUSRCLK_OUT => gt1_rxusrclk_i,
1449  GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
1450  GT1_RXOUTCLK_IN => gt1_rxoutclk_i,
1451 
1452  GT2_TXUSRCLK_OUT => gt2_txusrclk_i,
1453  GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
1454  GT2_TXOUTCLK_IN => gt2_txoutclk_i,
1455  GT2_RXUSRCLK_OUT => gt2_rxusrclk_i,
1456  GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
1457  GT2_RXOUTCLK_IN => gt2_rxoutclk_i,
1458 
1459  GT3_TXUSRCLK_OUT => gt3_txusrclk_i,
1460  GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
1461  GT3_TXOUTCLK_IN => gt3_txoutclk_i,
1462  GT3_RXUSRCLK_OUT => gt3_rxusrclk_i,
1463  GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
1464  GT3_RXOUTCLK_IN => gt3_rxoutclk_i,
1465  Q1_CLK0_GTREFCLK_PAD_N_IN => Q1_CLK0_GTREFCLK_PAD_N_IN,
1466  Q1_CLK0_GTREFCLK_PAD_P_IN => Q1_CLK0_GTREFCLK_PAD_P_IN,
1467  Q1_CLK0_GTREFCLK_OUT => q1_clk0_refclk_i
1468 
1469  );
1470 
1471 sysclk_in_i <= sysclk_in;
1472 
1473  common0_i:MGT_TX_RX_6G4_common
1474  generic map
1475  (
1476  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
1477  SIM_QPLLREFCLK_SEL => "001"
1478  )
1479  port map
1480  (
1481  QPLLREFCLKSEL_IN => "001",
1482  GTREFCLK0_IN => tied_to_ground_i,
1483  GTREFCLK1_IN => tied_to_ground_i,
1484  QPLLLOCK_OUT => gt0_qplllock_i,
1485  QPLLLOCKDETCLK_IN => sysclk_in_i,
1486  QPLLOUTCLK_OUT => gt0_qplloutclk_i,
1487  QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
1488  QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
1489  QPLLRESET_IN => gt0_qpllreset_t
1490 
1491 );
1492 
1493  common_reset_i:MGT_TX_RX_6G4_common_reset
1494  generic map
1495  (
1496  STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
1497  )
1498  port map
1499  (
1500  STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
1501  SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
1502  COMMON_RESET => commonreset_i --Reset QPLL
1503  );
1504 
1505 
1506  MGT_TX_RX_6G4_init_i : MGT_TX_RX_6G4
1507  port map
1508  (
1509  sysclk_in => sysclk_in_i,
1510  soft_reset_tx_in => SOFT_RESET_TX_IN,
1511  soft_reset_rx_in => SOFT_RESET_RX_IN,
1512  dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
1513  gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
1514  gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
1515  gt0_data_valid_in => gt0_data_valid_in,
1516  gt1_tx_fsm_reset_done_out => gt1_tx_fsm_reset_done_out,
1517  gt1_rx_fsm_reset_done_out => gt1_rx_fsm_reset_done_out,
1518  gt1_data_valid_in => gt1_data_valid_in,
1519  gt2_tx_fsm_reset_done_out => gt2_tx_fsm_reset_done_out,
1520  gt2_rx_fsm_reset_done_out => gt2_rx_fsm_reset_done_out,
1521  gt2_data_valid_in => gt2_data_valid_in,
1522  gt3_tx_fsm_reset_done_out => gt3_tx_fsm_reset_done_out,
1523  gt3_rx_fsm_reset_done_out => gt3_rx_fsm_reset_done_out,
1524  gt3_data_valid_in => gt3_data_valid_in,
1525 
1526  --_____________________________________________________________________
1527  --_____________________________________________________________________
1528  --GT0 (X1Y4)
1529 
1530  --------------------------------- CPLL Ports -------------------------------
1531  gt0_cpllfbclklost_out => gt0_cpllfbclklost_out,
1532  gt0_cplllock_out => gt0_cplllock_out,
1533  gt0_cplllockdetclk_in => sysclk_in_i,
1534  gt0_cpllreset_in => gt0_cpllreset_in,
1535  -------------------------- Channel - Clocking Ports ------------------------
1536  gt0_gtrefclk0_in => q1_clk0_refclk_i,
1537  gt0_gtrefclk1_in => tied_to_ground_i,
1538  ---------------------------- Channel - DRP Ports --------------------------
1539  gt0_drpaddr_in => gt0_drpaddr_in,
1540  gt0_drpclk_in => sysclk_in_i,
1541  gt0_drpdi_in => gt0_drpdi_in,
1542  gt0_drpdo_out => gt0_drpdo_out,
1543  gt0_drpen_in => gt0_drpen_in,
1544  gt0_drprdy_out => gt0_drprdy_out,
1545  gt0_drpwe_in => gt0_drpwe_in,
1546  ------------------------------- Loopback Ports -----------------------------
1547  gt0_loopback_in => gt0_loopback_in,
1548  ------------------------------ Power-Down Ports ----------------------------
1549  gt0_rxpd_in => gt0_rxpd_in,
1550  gt0_txpd_in => gt0_txpd_in,
1551  --------------------- RX Initialization and Reset Ports --------------------
1552  gt0_eyescanreset_in => gt0_eyescanreset_in,
1553  gt0_rxuserrdy_in => gt0_rxuserrdy_in,
1554  -------------------------- RX Margin Analysis Ports ------------------------
1555  gt0_eyescandataerror_out => gt0_eyescandataerror_out,
1556  gt0_eyescantrigger_in => gt0_eyescantrigger_in,
1557  ------------------- Receive Ports - Digital Monitor Ports ------------------
1558  gt0_dmonitorout_out => gt0_dmonitorout_out,
1559  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1560  gt0_rxusrclk_in => gt0_rxusrclk_i,
1561  gt0_rxusrclk2_in => gt0_rxusrclk2_i,
1562  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1563  gt0_rxdata_out => gt0_rxdata_out,
1564  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1565  gt0_rxdisperr_out => gt0_rxdisperr_out,
1566  gt0_rxnotintable_out => gt0_rxnotintable_out,
1567  ------------------------ Receive Ports - RX AFE Ports ----------------------
1568  gt0_gthrxn_in => gt0_gthrxn_in,
1569  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1570  gt0_rxphmonitor_out => gt0_rxphmonitor_out,
1571  gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
1572  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1573  gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
1574  gt0_rxbyterealign_out => gt0_rxbyterealign_out,
1575  gt0_rxcommadet_out => gt0_rxcommadet_out,
1576  --------------------- Receive Ports - RX Equalizer Ports -------------------
1577  gt0_rxmonitorout_out => gt0_rxmonitorout_out,
1578  gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
1579  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1580  gt0_rxoutclk_out => gt0_rxoutclk_i,
1581  gt0_rxoutclkfabric_out => gt0_rxoutclkfabric_out,
1582  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1583  gt0_gtrxreset_in => gt0_gtrxreset_in,
1584  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1585  gt0_rxchariscomma_out => gt0_rxchariscomma_out,
1586  gt0_rxcharisk_out => gt0_rxcharisk_out,
1587  ------------------------ Receive Ports -RX AFE Ports -----------------------
1588  gt0_gthrxp_in => gt0_gthrxp_in,
1589  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1590  gt0_rxresetdone_out => gt0_rxresetdone_out,
1591  --------------------- TX Initialization and Reset Ports --------------------
1592  gt0_gttxreset_in => gt0_gttxreset_in,
1593  gt0_txuserrdy_in => gt0_txuserrdy_in,
1594  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1595  gt0_txusrclk_in => gt0_txusrclk_i,
1596  gt0_txusrclk2_in => gt0_txusrclk2_i,
1597  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1598  gt0_txbufstatus_out => gt0_txbufstatus_out,
1599  ------------------ Transmit Ports - TX Data Path interface -----------------
1600  gt0_txdata_in => gt0_txdata_in,
1601  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1602  gt0_gthtxn_out => gt0_gthtxn_out,
1603  gt0_gthtxp_out => gt0_gthtxp_out,
1604  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1605  gt0_txoutclk_out => gt0_txoutclk_i,
1606  gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
1607  gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
1608  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1609  gt0_txresetdone_out => gt0_txresetdone_out,
1610  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1611  gt0_txcharisk_in => gt0_txcharisk_in,
1612 
1613 
1614 
1615  --_____________________________________________________________________
1616  --_____________________________________________________________________
1617  --GT1 (X1Y5)
1618 
1619  --------------------------------- CPLL Ports -------------------------------
1620  gt1_cpllfbclklost_out => gt1_cpllfbclklost_out,
1621  gt1_cplllock_out => gt1_cplllock_out,
1622  gt1_cplllockdetclk_in => sysclk_in_i,
1623  gt1_cpllreset_in => gt1_cpllreset_in,
1624  -------------------------- Channel - Clocking Ports ------------------------
1625  gt1_gtrefclk0_in => q1_clk0_refclk_i,
1626  gt1_gtrefclk1_in => tied_to_ground_i,
1627  ---------------------------- Channel - DRP Ports --------------------------
1628  gt1_drpaddr_in => gt1_drpaddr_in,
1629  gt1_drpclk_in => sysclk_in_i,
1630  gt1_drpdi_in => gt1_drpdi_in,
1631  gt1_drpdo_out => gt1_drpdo_out,
1632  gt1_drpen_in => gt1_drpen_in,
1633  gt1_drprdy_out => gt1_drprdy_out,
1634  gt1_drpwe_in => gt1_drpwe_in,
1635  ------------------------------- Loopback Ports -----------------------------
1636  gt1_loopback_in => gt1_loopback_in,
1637  ------------------------------ Power-Down Ports ----------------------------
1638  gt1_rxpd_in => gt1_rxpd_in,
1639  gt1_txpd_in => gt1_txpd_in,
1640  --------------------- RX Initialization and Reset Ports --------------------
1641  gt1_eyescanreset_in => gt1_eyescanreset_in,
1642  gt1_rxuserrdy_in => gt1_rxuserrdy_in,
1643  -------------------------- RX Margin Analysis Ports ------------------------
1644  gt1_eyescandataerror_out => gt1_eyescandataerror_out,
1645  gt1_eyescantrigger_in => gt1_eyescantrigger_in,
1646  ------------------- Receive Ports - Digital Monitor Ports ------------------
1647  gt1_dmonitorout_out => gt1_dmonitorout_out,
1648  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1649  gt1_rxusrclk_in => gt1_rxusrclk_i,
1650  gt1_rxusrclk2_in => gt1_rxusrclk2_i,
1651  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1652  gt1_rxdata_out => gt1_rxdata_out,
1653  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1654  gt1_rxdisperr_out => gt1_rxdisperr_out,
1655  gt1_rxnotintable_out => gt1_rxnotintable_out,
1656  ------------------------ Receive Ports - RX AFE Ports ----------------------
1657  gt1_gthrxn_in => gt1_gthrxn_in,
1658  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1659  gt1_rxphmonitor_out => gt1_rxphmonitor_out,
1660  gt1_rxphslipmonitor_out => gt1_rxphslipmonitor_out,
1661  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1662  gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
1663  gt1_rxbyterealign_out => gt1_rxbyterealign_out,
1664  gt1_rxcommadet_out => gt1_rxcommadet_out,
1665  --------------------- Receive Ports - RX Equalizer Ports -------------------
1666  gt1_rxmonitorout_out => gt1_rxmonitorout_out,
1667  gt1_rxmonitorsel_in => gt1_rxmonitorsel_in,
1668  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1669  gt1_rxoutclk_out => gt1_rxoutclk_i,
1670  gt1_rxoutclkfabric_out => gt1_rxoutclkfabric_out,
1671  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1672  gt1_gtrxreset_in => gt1_gtrxreset_in,
1673  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1674  gt1_rxchariscomma_out => gt1_rxchariscomma_out,
1675  gt1_rxcharisk_out => gt1_rxcharisk_out,
1676  ------------------------ Receive Ports -RX AFE Ports -----------------------
1677  gt1_gthrxp_in => gt1_gthrxp_in,
1678  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1679  gt1_rxresetdone_out => gt1_rxresetdone_out,
1680  --------------------- TX Initialization and Reset Ports --------------------
1681  gt1_gttxreset_in => gt1_gttxreset_in,
1682  gt1_txuserrdy_in => gt1_txuserrdy_in,
1683  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1684  gt1_txusrclk_in => gt1_txusrclk_i,
1685  gt1_txusrclk2_in => gt1_txusrclk2_i,
1686  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1687  gt1_txbufstatus_out => gt1_txbufstatus_out,
1688  ------------------ Transmit Ports - TX Data Path interface -----------------
1689  gt1_txdata_in => gt1_txdata_in,
1690  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1691  gt1_gthtxn_out => gt1_gthtxn_out,
1692  gt1_gthtxp_out => gt1_gthtxp_out,
1693  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1694  gt1_txoutclk_out => gt1_txoutclk_i,
1695  gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
1696  gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
1697  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1698  gt1_txresetdone_out => gt1_txresetdone_out,
1699  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1700  gt1_txcharisk_in => gt1_txcharisk_in,
1701 
1702 
1703 
1704  --_____________________________________________________________________
1705  --_____________________________________________________________________
1706  --GT2 (X1Y6)
1707 
1708  --------------------------------- CPLL Ports -------------------------------
1709  gt2_cpllfbclklost_out => gt2_cpllfbclklost_out,
1710  gt2_cplllock_out => gt2_cplllock_out,
1711  gt2_cplllockdetclk_in => sysclk_in_i,
1712  gt2_cpllreset_in => gt2_cpllreset_in,
1713  -------------------------- Channel - Clocking Ports ------------------------
1714  gt2_gtrefclk0_in => q1_clk0_refclk_i,
1715  gt2_gtrefclk1_in => tied_to_ground_i,
1716  ---------------------------- Channel - DRP Ports --------------------------
1717  gt2_drpaddr_in => gt2_drpaddr_in,
1718  gt2_drpclk_in => sysclk_in_i,
1719  gt2_drpdi_in => gt2_drpdi_in,
1720  gt2_drpdo_out => gt2_drpdo_out,
1721  gt2_drpen_in => gt2_drpen_in,
1722  gt2_drprdy_out => gt2_drprdy_out,
1723  gt2_drpwe_in => gt2_drpwe_in,
1724  ------------------------------- Loopback Ports -----------------------------
1725  gt2_loopback_in => gt2_loopback_in,
1726  ------------------------------ Power-Down Ports ----------------------------
1727  gt2_rxpd_in => gt2_rxpd_in,
1728  gt2_txpd_in => gt2_txpd_in,
1729  --------------------- RX Initialization and Reset Ports --------------------
1730  gt2_eyescanreset_in => gt2_eyescanreset_in,
1731  gt2_rxuserrdy_in => gt2_rxuserrdy_in,
1732  -------------------------- RX Margin Analysis Ports ------------------------
1733  gt2_eyescandataerror_out => gt2_eyescandataerror_out,
1734  gt2_eyescantrigger_in => gt2_eyescantrigger_in,
1735  ------------------- Receive Ports - Digital Monitor Ports ------------------
1736  gt2_dmonitorout_out => gt2_dmonitorout_out,
1737  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1738  gt2_rxusrclk_in => gt2_rxusrclk_i,
1739  gt2_rxusrclk2_in => gt2_rxusrclk2_i,
1740  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1741  gt2_rxdata_out => gt2_rxdata_out,
1742  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1743  gt2_rxdisperr_out => gt2_rxdisperr_out,
1744  gt2_rxnotintable_out => gt2_rxnotintable_out,
1745  ------------------------ Receive Ports - RX AFE Ports ----------------------
1746  gt2_gthrxn_in => gt2_gthrxn_in,
1747  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1748  gt2_rxphmonitor_out => gt2_rxphmonitor_out,
1749  gt2_rxphslipmonitor_out => gt2_rxphslipmonitor_out,
1750  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1751  gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
1752  gt2_rxbyterealign_out => gt2_rxbyterealign_out,
1753  gt2_rxcommadet_out => gt2_rxcommadet_out,
1754  --------------------- Receive Ports - RX Equalizer Ports -------------------
1755  gt2_rxmonitorout_out => gt2_rxmonitorout_out,
1756  gt2_rxmonitorsel_in => gt2_rxmonitorsel_in,
1757  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1758  gt2_rxoutclk_out => gt2_rxoutclk_i,
1759  gt2_rxoutclkfabric_out => gt2_rxoutclkfabric_out,
1760  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1761  gt2_gtrxreset_in => gt2_gtrxreset_in,
1762  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1763  gt2_rxchariscomma_out => gt2_rxchariscomma_out,
1764  gt2_rxcharisk_out => gt2_rxcharisk_out,
1765  ------------------------ Receive Ports -RX AFE Ports -----------------------
1766  gt2_gthrxp_in => gt2_gthrxp_in,
1767  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1768  gt2_rxresetdone_out => gt2_rxresetdone_out,
1769  --------------------- TX Initialization and Reset Ports --------------------
1770  gt2_gttxreset_in => gt2_gttxreset_in,
1771  gt2_txuserrdy_in => gt2_txuserrdy_in,
1772  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1773  gt2_txusrclk_in => gt2_txusrclk_i,
1774  gt2_txusrclk2_in => gt2_txusrclk2_i,
1775  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1776  gt2_txbufstatus_out => gt2_txbufstatus_out,
1777  ------------------ Transmit Ports - TX Data Path interface -----------------
1778  gt2_txdata_in => gt2_txdata_in,
1779  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1780  gt2_gthtxn_out => gt2_gthtxn_out,
1781  gt2_gthtxp_out => gt2_gthtxp_out,
1782  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1783  gt2_txoutclk_out => gt2_txoutclk_i,
1784  gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
1785  gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
1786  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1787  gt2_txresetdone_out => gt2_txresetdone_out,
1788  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1789  gt2_txcharisk_in => gt2_txcharisk_in,
1790 
1791 
1792 
1793  --_____________________________________________________________________
1794  --_____________________________________________________________________
1795  --GT3 (X1Y7)
1796 
1797  --------------------------------- CPLL Ports -------------------------------
1798  gt3_cpllfbclklost_out => gt3_cpllfbclklost_out,
1799  gt3_cplllock_out => gt3_cplllock_out,
1800  gt3_cplllockdetclk_in => sysclk_in_i,
1801  gt3_cpllreset_in => gt3_cpllreset_in,
1802  -------------------------- Channel - Clocking Ports ------------------------
1803  gt3_gtrefclk0_in => q1_clk0_refclk_i,
1804  gt3_gtrefclk1_in => tied_to_ground_i,
1805  ---------------------------- Channel - DRP Ports --------------------------
1806  gt3_drpaddr_in => gt3_drpaddr_in,
1807  gt3_drpclk_in => sysclk_in_i,
1808  gt3_drpdi_in => gt3_drpdi_in,
1809  gt3_drpdo_out => gt3_drpdo_out,
1810  gt3_drpen_in => gt3_drpen_in,
1811  gt3_drprdy_out => gt3_drprdy_out,
1812  gt3_drpwe_in => gt3_drpwe_in,
1813  ------------------------------- Loopback Ports -----------------------------
1814  gt3_loopback_in => gt3_loopback_in,
1815  ------------------------------ Power-Down Ports ----------------------------
1816  gt3_rxpd_in => gt3_rxpd_in,
1817  gt3_txpd_in => gt3_txpd_in,
1818  --------------------- RX Initialization and Reset Ports --------------------
1819  gt3_eyescanreset_in => gt3_eyescanreset_in,
1820  gt3_rxuserrdy_in => gt3_rxuserrdy_in,
1821  -------------------------- RX Margin Analysis Ports ------------------------
1822  gt3_eyescandataerror_out => gt3_eyescandataerror_out,
1823  gt3_eyescantrigger_in => gt3_eyescantrigger_in,
1824  ------------------- Receive Ports - Digital Monitor Ports ------------------
1825  gt3_dmonitorout_out => gt3_dmonitorout_out,
1826  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1827  gt3_rxusrclk_in => gt3_rxusrclk_i,
1828  gt3_rxusrclk2_in => gt3_rxusrclk2_i,
1829  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1830  gt3_rxdata_out => gt3_rxdata_out,
1831  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1832  gt3_rxdisperr_out => gt3_rxdisperr_out,
1833  gt3_rxnotintable_out => gt3_rxnotintable_out,
1834  ------------------------ Receive Ports - RX AFE Ports ----------------------
1835  gt3_gthrxn_in => gt3_gthrxn_in,
1836  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1837  gt3_rxphmonitor_out => gt3_rxphmonitor_out,
1838  gt3_rxphslipmonitor_out => gt3_rxphslipmonitor_out,
1839  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1840  gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
1841  gt3_rxbyterealign_out => gt3_rxbyterealign_out,
1842  gt3_rxcommadet_out => gt3_rxcommadet_out,
1843  --------------------- Receive Ports - RX Equalizer Ports -------------------
1844  gt3_rxmonitorout_out => gt3_rxmonitorout_out,
1845  gt3_rxmonitorsel_in => gt3_rxmonitorsel_in,
1846  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1847  gt3_rxoutclk_out => gt3_rxoutclk_i,
1848  gt3_rxoutclkfabric_out => gt3_rxoutclkfabric_out,
1849  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1850  gt3_gtrxreset_in => gt3_gtrxreset_in,
1851  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1852  gt3_rxchariscomma_out => gt3_rxchariscomma_out,
1853  gt3_rxcharisk_out => gt3_rxcharisk_out,
1854  ------------------------ Receive Ports -RX AFE Ports -----------------------
1855  gt3_gthrxp_in => gt3_gthrxp_in,
1856  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1857  gt3_rxresetdone_out => gt3_rxresetdone_out,
1858  --------------------- TX Initialization and Reset Ports --------------------
1859  gt3_gttxreset_in => gt3_gttxreset_in,
1860  gt3_txuserrdy_in => gt3_txuserrdy_in,
1861  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1862  gt3_txusrclk_in => gt3_txusrclk_i,
1863  gt3_txusrclk2_in => gt3_txusrclk2_i,
1864  ---------------------- Transmit Ports - TX Buffer Ports --------------------
1865  gt3_txbufstatus_out => gt3_txbufstatus_out,
1866  ------------------ Transmit Ports - TX Data Path interface -----------------
1867  gt3_txdata_in => gt3_txdata_in,
1868  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1869  gt3_gthtxn_out => gt3_gthtxn_out,
1870  gt3_gthtxp_out => gt3_gthtxp_out,
1871  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1872  gt3_txoutclk_out => gt3_txoutclk_i,
1873  gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
1874  gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
1875  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1876  gt3_txresetdone_out => gt3_txresetdone_out,
1877  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1878  gt3_txcharisk_in => gt3_txcharisk_in,
1879 
1880 
1881 
1882  gt0_qplloutclk_in => gt0_qplloutclk_i,
1883  gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
1884  );
1885 
1886 
1887 
1888 end RTL;
1889 
MGT_TX_RX_6G4_GT_USRCLK_SOURCE
Definition: mgt_tx_rx_6g4_gt_usrclk_source.vhd:72
MGT_TX_RX_6G4_common_reset
Definition: mgt_tx_rx_6g4_common_reset.vhd:78
MGT_TX_RX_6G4_common
Definition: mgt_tx_rx_6g4_common.vhd:70
MGT_TX_RX_6G4_support.RTL
Definition: mgt_tx_rx_6g4_support.vhd:420
MGT_TX_RX_6G4_support
Definition: mgt_tx_rx_6g4_support.vhd:74
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