MGT_TX_RX_6G4_common Entity Reference

Inheritance diagram for MGT_TX_RX_6G4_common:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
WRAPPER_SIM_GTRESET_SPEEDUP	string := " TRUE "
SIM_QPLLREFCLK_SEL	bit_vector := " 001 "

Ports
QPLLREFCLKSEL_IN	in	std_logic_vector ( 2 downto 0 )
GTREFCLK1_IN	in	std_logic
GTREFCLK0_IN	in	std_logic
QPLLLOCK_OUT	out	std_logic
QPLLLOCKDETCLK_IN	in	std_logic
QPLLOUTCLK_OUT	out	std_logic
QPLLOUTREFCLK_OUT	out	std_logic
QPLLREFCLKLOST_OUT	out	std_logic
QPLLRESET_IN	in	std_logic

Detailed Description

Definition at line 70 of file mgt_tx_rx_6g4_common.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd