RTL Architecture Reference

Functions
bit_vector	conv_qpll_fbdiv_top ( qpllfbdiv_top: in in integer )	[ impure ]
bit	conv_qpll_fbdiv_ratio ( qpllfbdiv_top: in in integer )	[ impure ]

Constants
QPLL_FBDIV_TOP	integer := 16
QPLL_FBDIV_IN	bit_vector ( 9 downto 0 ) := conv_qpll_fbdiv_top ( QPLL_FBDIV_TOP )
QPLL_FBDIV_RATIO	bit := conv_qpll_fbdiv_ratio ( QPLL_FBDIV_TOP )

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
tied_to_vcc_vec_i	std_logic_vector ( 63 downto 0 )

Attributes
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	architecture is " MGT_TX_RX_6G4_common , gtwizard_v3_6_11 , {protocol_file = Start_from_scratch} "

Instantiations
gthe2_common_i	gthe2_common

Detailed Description

Definition at line 92 of file mgt_tx_rx_6g4_common.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_common.vhd