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ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt_tx_rx_6g4_common.vhd
1 ------------------------------------------------------------------------------/
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : mgt_tx_rx_6g4_common.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module MGT_TX_RX_6G4_common
14 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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62 
63 library ieee;
64 use ieee.std_logic_1164.all;
65 use ieee.numeric_std.all;
66 library UNISIM;
67 use UNISIM.VCOMPONENTS.ALL;
68 
69 --***************************** Entity Declaration ****************************
70 entity MGT_TX_RX_6G4_common is
71 generic
72 (
73  -- Simulation attributes
74  WRAPPER_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- Set to "true" to speed up sim reset
75  SIM_QPLLREFCLK_SEL : bit_vector := "001"
76 );
77 port
78 (
79  QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
80  GTREFCLK1_IN : in std_logic;
81  GTREFCLK0_IN : in std_logic;
82  QPLLLOCK_OUT : out std_logic;
83  QPLLLOCKDETCLK_IN : in std_logic;
84  QPLLOUTCLK_OUT : out std_logic;
85  QPLLOUTREFCLK_OUT : out std_logic;
86  QPLLREFCLKLOST_OUT : out std_logic;
87  QPLLRESET_IN : in std_logic
88 );
89 
90 end MGT_TX_RX_6G4_common;
91 
92 architecture RTL of MGT_TX_RX_6G4_common is
93 
94  attribute CORE_GENERATION_INFO : string;
95  attribute CORE_GENERATION_INFO of RTL : architecture is "MGT_TX_RX_6G4_common,gtwizard_v3_6_11,{protocol_file=Start_from_scratch}";
96 
97 
98 --*************************Logic to set Attribute QPLL_FB_DIV*****************************
99  impure function conv_qpll_fbdiv_top (qpllfbdiv_top : in integer) return bit_vector is
100  begin
101  if (qpllfbdiv_top = 16) then
102  return "0000100000";
103  elsif (qpllfbdiv_top = 20) then
104  return "0000110000" ;
105  elsif (qpllfbdiv_top = 32) then
106  return "0001100000" ;
107  elsif (qpllfbdiv_top = 40) then
108  return "0010000000" ;
109  elsif (qpllfbdiv_top = 64) then
110  return "0011100000" ;
111  elsif (qpllfbdiv_top = 66) then
112  return "0101000000" ;
113  elsif (qpllfbdiv_top = 80) then
114  return "0100100000" ;
115  elsif (qpllfbdiv_top = 100) then
116  return "0101110000" ;
117  else
118  return "0000000000" ;
119  end if;
120  end function;
121 
122  impure function conv_qpll_fbdiv_ratio (qpllfbdiv_top : in integer) return bit is
123  begin
124  if (qpllfbdiv_top = 16) then
125  return '1';
126  elsif (qpllfbdiv_top = 20) then
127  return '1' ;
128  elsif (qpllfbdiv_top = 32) then
129  return '1' ;
130  elsif (qpllfbdiv_top = 40) then
131  return '1' ;
132  elsif (qpllfbdiv_top = 64) then
133  return '1' ;
134  elsif (qpllfbdiv_top = 66) then
135  return '0' ;
136  elsif (qpllfbdiv_top = 80) then
137  return '1' ;
138  elsif (qpllfbdiv_top = 100) then
139  return '1' ;
140  else
141  return '1' ;
142  end if;
143  end function;
144  constant QPLL_FBDIV_TOP : integer := 16;
145  constant QPLL_FBDIV_IN : bit_vector(9 downto 0) := conv_qpll_fbdiv_top(QPLL_FBDIV_TOP);
146  constant QPLL_FBDIV_RATIO : bit := conv_qpll_fbdiv_ratio(QPLL_FBDIV_TOP);
147 
148  -- ground and tied_to_vcc_i signals
149  signal tied_to_ground_i : std_logic;
150  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
151  signal tied_to_vcc_i : std_logic;
152  signal tied_to_vcc_vec_i : std_logic_vector(63 downto 0);
153 begin
154 
155  tied_to_ground_i <= '0';
156  tied_to_ground_vec_i(63 downto 0) <= (others => '0');
157  tied_to_vcc_i <= '1';
158  tied_to_vcc_vec_i(63 downto 0) <= (others => '1');
159 
160  --_________________________________________________________________________
161  --_________________________________________________________________________
162  --_________________________GTXE2_COMMON____________________________________
163 
164  gthe2_common_i : GTHE2_COMMON
165  generic map
166  (
167  -- Simulation attributes
168  SIM_RESET_SPEEDUP => WRAPPER_SIM_GTRESET_SPEEDUP,
169  SIM_QPLLREFCLK_SEL => (SIM_QPLLREFCLK_SEL),
170  SIM_VERSION => "2.0",
171 
172 
173  ------------------COMMON BLOCK Attributes---------------
174  BIAS_CFG => (x"0000040000001050"),
175  COMMON_CFG => (x"0000001C"),
176  QPLL_CFG => (x"04801C7"),
177  QPLL_CLKOUT_CFG => ("1111"),
178  QPLL_COARSE_FREQ_OVRD => ("010000"),
179  QPLL_COARSE_FREQ_OVRD_EN => ('0'),
180  QPLL_CP => ("0000011111"),
181  QPLL_CP_MONITOR_EN => ('0'),
182  QPLL_DMONITOR_SEL => ('0'),
183  QPLL_FBDIV => (QPLL_FBDIV_IN),
184  QPLL_FBDIV_MONITOR_EN => ('0'),
185  QPLL_FBDIV_RATIO => (QPLL_FBDIV_RATIO),
186  QPLL_INIT_CFG => (x"000006"),
187  QPLL_LOCK_CFG => (x"05E8"),
188  QPLL_LPF => ("1111"),
189  QPLL_REFCLK_DIV => (1),
190  RSVD_ATTR0 => (x"0000"),
191  RSVD_ATTR1 => (x"0000"),
192  QPLL_RP_COMP => ('0'),
193  QPLL_VTRL_RESET => ("00"),
194  RCAL_CFG => ("00")
195 
196 
197  )
198  port map
199  (
200  ------------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
201  DRPADDR => tied_to_ground_vec_i(7 downto 0),
202  DRPCLK => tied_to_ground_i,
203  DRPDI => tied_to_ground_vec_i(15 downto 0),
204  DRPDO => open,
205  DRPEN => tied_to_ground_i,
206  DRPRDY => open,
207  DRPWE => tied_to_ground_i,
208  ---------------------- Common Block - Ref Clock Ports ---------------------
209  GTGREFCLK => tied_to_ground_i,
210  GTNORTHREFCLK0 => tied_to_ground_i,
211  GTNORTHREFCLK1 => tied_to_ground_i,
212  GTREFCLK0 => GTREFCLK0_IN,
213  GTREFCLK1 => GTREFCLK1_IN,
214  GTSOUTHREFCLK0 => tied_to_ground_i,
215  GTSOUTHREFCLK1 => tied_to_ground_i,
216  ------------------------- Common Block - QPLL Ports -----------------------
217  QPLLDMONITOR => open,
218  ----------------------- Common Block - Clocking Ports ----------------------
219  QPLLOUTCLK => QPLLOUTCLK_OUT,
220  QPLLOUTREFCLK => QPLLOUTREFCLK_OUT,
221  REFCLKOUTMONITOR => open,
222  ------------------------- Common Block - QPLL Ports ------------------------
223  BGRCALOVRDENB => tied_to_vcc_i,
224  PMARSVDOUT => open,
225  QPLLFBCLKLOST => open,
226  QPLLLOCK => QPLLLOCK_OUT,
227  QPLLLOCKDETCLK => QPLLLOCKDETCLK_IN,
228  QPLLLOCKEN => tied_to_vcc_i,
229  QPLLOUTRESET => tied_to_ground_i,
230  QPLLPD => tied_to_vcc_i,
231  QPLLREFCLKLOST => QPLLREFCLKLOST_OUT,
232  QPLLREFCLKSEL => QPLLREFCLKSEL_IN,
233  QPLLRESET => QPLLRESET_IN,
234  QPLLRSVD1 => "0000000000000000",
235  QPLLRSVD2 => "11111",
236  --------------------------------- QPLL Ports -------------------------------
237  BGBYPASSB => tied_to_vcc_i,
238  BGMONITORENB => tied_to_vcc_i,
239  BGPDB => tied_to_vcc_i,
240  BGRCALOVRD => "11111",
241  PMARSVD => "00000000",
242  RCALENB => tied_to_vcc_i
243 
244  );
245 end RTL;
MGT_TX_RX_6G4_common.RTL
Definition: mgt_tx_rx_6g4_common.vhd:92
MGT_TX_RX_6G4_common
Definition: mgt_tx_rx_6g4_common.vhd:70
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