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mgt_tx_rx_6g4_gt_usrclk_source.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : mgt_tx_rx_6g4_gt_usrclk_source.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 --
13 -- Module MGT_TX_RX_6G4_GT_USRCLK_SOURCE (for use with GTs)
14 -- Generated by Xilinx 7 Series FPGAs Transceivers 7 Series FPGAs Transceivers Wizard
15 --
16 --
17 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
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62 
63 
64 library ieee;
65 use ieee.std_logic_1164.all;
66 use ieee.numeric_std.all;
67 use ieee.std_logic_unsigned.all;
68 library UNISIM;
69 use UNISIM.VCOMPONENTS.ALL;
70 
71 --***********************************Entity Declaration*******************************
72 entity MGT_TX_RX_6G4_GT_USRCLK_SOURCE is
73 port
74 (
75 
76  GT0_TXUSRCLK_OUT : out std_logic;
77  GT0_TXUSRCLK2_OUT : out std_logic;
78  GT0_TXOUTCLK_IN : in std_logic;
79  GT0_RXUSRCLK_OUT : out std_logic;
80  GT0_RXUSRCLK2_OUT : out std_logic;
81  GT0_RXOUTCLK_IN : in std_logic;
82 
83  GT1_TXUSRCLK_OUT : out std_logic;
84  GT1_TXUSRCLK2_OUT : out std_logic;
85  GT1_TXOUTCLK_IN : in std_logic;
86  GT1_RXUSRCLK_OUT : out std_logic;
87  GT1_RXUSRCLK2_OUT : out std_logic;
88  GT1_RXOUTCLK_IN : in std_logic;
89 
90  GT2_TXUSRCLK_OUT : out std_logic;
91  GT2_TXUSRCLK2_OUT : out std_logic;
92  GT2_TXOUTCLK_IN : in std_logic;
93  GT2_RXUSRCLK_OUT : out std_logic;
94  GT2_RXUSRCLK2_OUT : out std_logic;
95  GT2_RXOUTCLK_IN : in std_logic;
96 
97  GT3_TXUSRCLK_OUT : out std_logic;
98  GT3_TXUSRCLK2_OUT : out std_logic;
99  GT3_TXOUTCLK_IN : in std_logic;
100  GT3_RXUSRCLK_OUT : out std_logic;
101  GT3_RXUSRCLK2_OUT : out std_logic;
102  GT3_RXOUTCLK_IN : in std_logic;
103  Q1_CLK0_GTREFCLK_PAD_N_IN : in std_logic;
104  Q1_CLK0_GTREFCLK_PAD_P_IN : in std_logic;
105  Q1_CLK0_GTREFCLK_OUT : out std_logic
106 );
107 
108 
109 end MGT_TX_RX_6G4_GT_USRCLK_SOURCE;
110 
111 architecture RTL of MGT_TX_RX_6G4_GT_USRCLK_SOURCE is
112 
113 component MGT_TX_RX_6G4_CLOCK_MODULE is
114 generic
115 (
116  MULT : real := 2.0;
117  DIVIDE : integer := 2;
118  CLK_PERIOD : real := 6.4;
119  OUT0_DIVIDE : real := 2.0;
120  OUT1_DIVIDE : integer := 2;
121  OUT2_DIVIDE : integer := 2;
122  OUT3_DIVIDE : integer := 2
123 );
124 port
125  (-- Clock in ports
126  CLK_IN : in std_logic;
127  -- Clock out ports
128  CLK0_OUT : out std_logic;
129  CLK1_OUT : out std_logic;
130  CLK2_OUT : out std_logic;
131  CLK3_OUT : out std_logic;
132  -- Status and control signals
133  MMCM_RESET_IN : in std_logic;
134  MMCM_LOCKED_OUT : out std_logic
135  );
136 end component;
137 
138 --*********************************Wire Declarations**********************************
139 
140  signal tied_to_ground_i : std_logic;
141  signal tied_to_vcc_i : std_logic;
142 
143  signal gt0_txoutclk_i : std_logic;
144  signal gt0_rxoutclk_i : std_logic;
145 
146  signal gt1_txoutclk_i : std_logic;
147  signal gt1_rxoutclk_i : std_logic;
148 
149  signal gt2_txoutclk_i : std_logic;
150  signal gt2_rxoutclk_i : std_logic;
151 
152  signal gt3_txoutclk_i : std_logic;
153  signal gt3_rxoutclk_i : std_logic;
154 
155  attribute syn_noclockbuf : boolean;
156  signal q1_clk0_gtrefclk : std_logic;
157  attribute syn_noclockbuf of q1_clk0_gtrefclk : signal is true;
158 
159  signal gt0_txusrclk_i : std_logic;
160  signal gt0_rxusrclk_i : std_logic;
161 
162 
163 begin
164 
165 --*********************************** Beginning of Code *******************************
166 
167  -- Static signal Assigments
168  tied_to_ground_i <= '0';
169  tied_to_vcc_i <= '1';
170  gt0_txoutclk_i <= GT0_TXOUTCLK_IN;
171  gt0_rxoutclk_i <= GT0_RXOUTCLK_IN;
172  gt1_txoutclk_i <= GT1_TXOUTCLK_IN;
173  gt1_rxoutclk_i <= GT1_RXOUTCLK_IN;
174  gt2_txoutclk_i <= GT2_TXOUTCLK_IN;
175  gt2_rxoutclk_i <= GT2_RXOUTCLK_IN;
176  gt3_txoutclk_i <= GT3_TXOUTCLK_IN;
177  gt3_rxoutclk_i <= GT3_RXOUTCLK_IN;
178 
179  Q1_CLK0_GTREFCLK_OUT <= q1_clk0_gtrefclk;
180 
181  --IBUFDS_GTE2
182  ibufds_instq1_clk0 : IBUFDS_GTE2
183  port map
184  (
185  O => q1_clk0_gtrefclk,
186  ODIV2 => open,
187  CEB => tied_to_ground_i,
188  I => Q1_CLK0_GTREFCLK_PAD_P_IN,
189  IB => Q1_CLK0_GTREFCLK_PAD_N_IN
190  );
191 
192 
193 
194  -- Instantiate a MMCM module to divide the reference clock. Uses internal feedback
195  -- for improved jitter performance, and to avoid consuming an additional BUFG
196  txoutclk_bufg0_i : BUFG
197  port map
198  (
199  I => gt0_txoutclk_i,
200  O => gt0_txusrclk_i
201  );
202 
203 
204  rxoutclk_bufg1_i : BUFG
205  port map
206  (
207  I => gt0_rxoutclk_i,
208  O => gt0_rxusrclk_i
209  );
210 
211 
212 
213 
214 GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
215 GT0_TXUSRCLK2_OUT <= gt0_txusrclk_i;
216 GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
217 GT0_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
218 
219 GT1_TXUSRCLK_OUT <= gt0_txusrclk_i;
220 GT1_TXUSRCLK2_OUT <= gt0_txusrclk_i;
221 GT1_RXUSRCLK_OUT <= gt0_rxusrclk_i;
222 GT1_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
223 
224 GT2_TXUSRCLK_OUT <= gt0_txusrclk_i;
225 GT2_TXUSRCLK2_OUT <= gt0_txusrclk_i;
226 GT2_RXUSRCLK_OUT <= gt0_rxusrclk_i;
227 GT2_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
228 
229 GT3_TXUSRCLK_OUT <= gt0_txusrclk_i;
230 GT3_TXUSRCLK2_OUT <= gt0_txusrclk_i;
231 GT3_RXUSRCLK_OUT <= gt0_rxusrclk_i;
232 GT3_RXUSRCLK2_OUT <= gt0_rxusrclk_i;
233 end RTL;
234 
MGT_TX_RX_6G4_GT_USRCLK_SOURCE.RTL
Definition: mgt_tx_rx_6g4_gt_usrclk_source.vhd:111
MGT_TX_RX_6G4_GT_USRCLK_SOURCE
Definition: mgt_tx_rx_6g4_gt_usrclk_source.vhd:72
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