RTL Architecture Reference

Components
MGT_TX_RX_6G4_CLOCK_MODULE

Signals
tied_to_ground_i	std_logic
tied_to_vcc_i	std_logic
gt0_txoutclk_i	std_logic
gt0_rxoutclk_i	std_logic
gt1_txoutclk_i	std_logic
gt1_rxoutclk_i	std_logic
gt2_txoutclk_i	std_logic
gt2_rxoutclk_i	std_logic
gt3_txoutclk_i	std_logic
gt3_rxoutclk_i	std_logic
q1_clk0_gtrefclk	std_logic
gt0_txusrclk_i	std_logic
gt0_rxusrclk_i	std_logic

Attributes
syn_noclockbuf	boolean
syn_noclockbuf	signal is true

Instantiations
ibufds_instq1_clk0	ibufds_gte2
txoutclk_bufg0_i	bufg
rxoutclk_bufg1_i	bufg

Detailed Description

Definition at line 111 of file mgt_tx_rx_6g4_gt_usrclk_source.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd