MGT_TX_RX_6G4_GT_USRCLK_SOURCE Entity Reference

Inheritance diagram for MGT_TX_RX_6G4_GT_USRCLK_SOURCE:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
std_logic_unsigned
VCOMPONENTS

Ports
GT0_TXUSRCLK_OUT	out	std_logic
GT0_TXUSRCLK2_OUT	out	std_logic
GT0_TXOUTCLK_IN	in	std_logic
GT0_RXUSRCLK_OUT	out	std_logic
GT0_RXUSRCLK2_OUT	out	std_logic
GT0_RXOUTCLK_IN	in	std_logic
GT1_TXUSRCLK_OUT	out	std_logic
GT1_TXUSRCLK2_OUT	out	std_logic
GT1_TXOUTCLK_IN	in	std_logic
GT1_RXUSRCLK_OUT	out	std_logic
GT1_RXUSRCLK2_OUT	out	std_logic
GT1_RXOUTCLK_IN	in	std_logic
GT2_TXUSRCLK_OUT	out	std_logic
GT2_TXUSRCLK2_OUT	out	std_logic
GT2_TXOUTCLK_IN	in	std_logic
GT2_RXUSRCLK_OUT	out	std_logic
GT2_RXUSRCLK2_OUT	out	std_logic
GT2_RXOUTCLK_IN	in	std_logic
GT3_TXUSRCLK_OUT	out	std_logic
GT3_TXUSRCLK2_OUT	out	std_logic
GT3_TXOUTCLK_IN	in	std_logic
GT3_RXUSRCLK_OUT	out	std_logic
GT3_RXUSRCLK2_OUT	out	std_logic
GT3_RXOUTCLK_IN	in	std_logic
Q1_CLK0_GTREFCLK_PAD_N_IN	in	std_logic
Q1_CLK0_GTREFCLK_PAD_P_IN	in	std_logic
Q1_CLK0_GTREFCLK_OUT	out	std_logic

Detailed Description

Definition at line 72 of file mgt_tx_rx_6g4_gt_usrclk_source.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_gt_usrclk_source.vhd