RTL Architecture Reference

mgt selection wrapper More...

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
tied_to_vcc_vec_i	std_logic_vector ( 7 downto 0 )
gt0_drpaddr_i	std_logic_vector ( 8 downto 0 )
gt0_drpdi_i	std_logic_vector ( 15 downto 0 )
gt0_drpdo_i	std_logic_vector ( 15 downto 0 )
gt0_drpen_i	std_logic
gt0_drprdy_i	std_logic
gt0_drpwe_i	std_logic
gt1_drpaddr_i	std_logic_vector ( 8 downto 0 )
gt1_drpdi_i	std_logic_vector ( 15 downto 0 )
gt1_drpdo_i	std_logic_vector ( 15 downto 0 )
gt1_drpen_i	std_logic
gt1_drprdy_i	std_logic
gt1_drpwe_i	std_logic
gt2_drpaddr_i	std_logic_vector ( 8 downto 0 )
gt2_drpdi_i	std_logic_vector ( 15 downto 0 )
gt2_drpdo_i	std_logic_vector ( 15 downto 0 )
gt2_drpen_i	std_logic
gt2_drprdy_i	std_logic
gt2_drpwe_i	std_logic
gt3_drpaddr_i	std_logic_vector ( 8 downto 0 )
gt3_drpdi_i	std_logic_vector ( 15 downto 0 )
gt3_drpdo_i	std_logic_vector ( 15 downto 0 )
gt3_drpen_i	std_logic
gt3_drprdy_i	std_logic
gt3_drpwe_i	std_logic

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	architecture is " yes "
CORE_GENERATION_INFO	string
CORE_GENERATION_INFO	architecture is " MGT_TX_RX_6G4 , gtwizard_v3_6_5 , {protocol_file = Start_from_scratch} "

Instantiations
min_latency_1_quad_rx_tx_support_i	MGT_TX_RX_6G4_support <Entity MGT_TX_RX_6G4_support>

Detailed Description

mgt selection wrapper

This module is the mgt wrapper of the control FPGa that create quad ports for selected quad and sets zero to the disabled quad ports in the design. This wrapper generate a quad with RX and TX at 6.4Gbps, Ref clk = 160MHz.

Author

Mohammed Siyad

Definition at line 221 of file mgt_tx_rx_6g4_wrapper.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/mgt/mgt_tx_rx_6g4_wrapper.vhd