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ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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mgt11g2_tx_rx_cfgpa_gen.vhd
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1 
7 
8 library IEEE;
9 use IEEE.STD_LOGIC_1164.all;
10 --library mgt_lib;
11 --use mgt_lib.mgt_type.all;
12 library work;
13 use work.mgt_type.all;
14 
16 entity mgt11g2_tx_rx_cfpga_gen is
17  generic(num_quad_tx_rx : natural:= 2 );
18 
19  port (
20  TTC_CLK : in std_logic;
21  MGT_CLK_GTREFCLK_PAD_N_IN : in std_logic_vector(num_quad_tx_rx-1 downto 0);
22  MGT_CLK_GTREFCLK_PAD_P_IN : in std_logic_vector(num_quad_tx_rx-1 downto 0);
23 
24  mgt_TXUSRCLK_OUT : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
25  mgt_RXUSRCLK_OUT : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
26 
27  mgt_SOFT_RESET_TX_IN : in std_logic_vector(num_quad_tx_rx -1 downto 0);
28  mgt_SOFT_RESET_RX_IN : in std_logic_vector(num_quad_tx_rx -1 downto 0);
29  -- data
30  RXN_IN : in mgt_rx_array(num_quad_tx_rx-1 downto 0);
31  RXP_IN : in mgt_rx_array(num_quad_tx_rx-1 downto 0);
32  TXN_IN : out mgt_tx_array(num_quad_tx_rx-1 downto 0);
33  TXP_IN : out mgt_tx_array(num_quad_tx_rx-1 downto 0);
34 
35  rxdata_quad_array : out mgt_rxdata_array (num_quad_tx_rx -1 downto 0);
36  txdata_quad_array : in mgt_txdata_array (num_quad_tx_rx -1 downto 0);
37  -- status and monitoring
38  mgt_DATA_VALID_IN : in std_logic_vector(4*num_quad_tx_rx -1 downto 0);
39  mgt_TX_FSM_RESET_DONE : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
40  mgt_RX_FSM_RESET_DONE : out std_logic_vector(4*num_quad_tx_rx -1 downto 0);
41  rxbyteisaligned_quad_array : out mgt_rxbyteisaligned_array(num_quad_tx_rx -1 downto 0);
42  rxresetdone_quad_array : out mgt_rxresetdone_array (num_quad_tx_rx -1 downto 0);
43  txresetdone_quad_array : out mgt_txresetdone_array (num_quad_tx_rx -1 downto 0);
44 
45  gt_rxpd_array : in mgt_rxpd_array (num_quad_tx_rx -1 downto 0);
46  gt_txpd_array : in mgt_txpd_array (num_quad_tx_rx -1 downto 0);
47  rxchariscomma_quad_array : out mgt_rxchariskcomm_array (num_quad_tx_rx -1 downto 0);
48  rxcharisk_quad_array : out mgt_rxcharisk_array (num_quad_tx_rx -1 downto 0);
49  txcharisk_quad_array : in mgt_txcharisk_array (num_quad_tx_rx -1 downto 0);
50  txbufstatus_quad_array : out mgt_txbufstatus_array (num_quad_tx_rx -1 downto 0);
51  rxbyterealign_quad_array : out mgt_rxbyterealign_array (num_quad_tx_rx -1 downto 0);
52  rxcommadet_quad_array : out mgt_rxcommadet_array (num_quad_tx_rx -1 downto 0);
53  rxdisperr_quad_array : out mgt_rxdisperr_array (num_quad_tx_rx -1 downto 0);
54  rxnotintable_quad_array : out mgt_rxnotintable_array (num_quad_tx_rx -1 downto 0);
55  mgt_QPLLREFCLKLOST_OUT : out std_logic_vector(num_quad_tx_rx-1 downto 0);
56  mgt_QPLLLOCK_OUT : out std_logic_vector (num_quad_tx_rx -1 downto 0)
57  );
58 end mgt11g2_tx_rx_cfpga_gen;
59 
61 architecture Behavioral of mgt11g2_tx_rx_cfpga_gen is
62 
63 --- mgt signal declarations
64 
65  signal RXN_IN_tx_rx, RXP_IN_tx_rx : mgt_rx_array (num_quad_tx_rx-1 downto 0);
66  signal TXN_IN_tx_rx, TXP_IN_tx_rx : mgt_tx_array (num_quad_tx_rx-1 downto 0);
67 
68 begin
69 
70  MGT_GEN : for i in 0 to num_quad_tx_rx-1
71  generate
72 
73  mgt_1quad_Rx_Tx : entity work.mgt11g2_tx_rx_cfpga_wrapper
74  -- This part will generate 2 quads, 2*4 = 8 mgts.
75 
76  port map (
77  --clk280 => clk280,
78  SOFT_RESET_TX_IN => mgt_SOFT_RESET_TX_IN(i),
79  SOFT_RESET_RX_IN => mgt_SOFT_RESET_RX_IN(i),
80  RXN_IN => RXN_IN(i).RXN_IN,
81  RXP_IN => RXP_IN(i).RXP_IN,
82  TXN_OUT => TXN_IN(i).TXN_OUT,
83  TXP_OUT => TXP_IN(i).TXP_OUT,
84  Q1_CLK1_GTREFCLK_PAD_N_IN => MGT_CLK_GTREFCLK_PAD_N_IN(i),
85  Q1_CLK1_GTREFCLK_PAD_P_IN => MGT_CLK_GTREFCLK_PAD_P_IN(i),
86 
87  GT0_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i),
88  GT0_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i),
89  GT0_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i),
90 
91  GT1_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i+1),
92  GT1_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i+1),
93  GT1_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i+1),
94 
95  GT2_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i+2),
96  GT2_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i+2),
97  GT2_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i+2),
98 
99  GT3_TX_FSM_RESET_DONE_OUT => mgt_TX_FSM_RESET_DONE(4*i+3),
100  GT3_RX_FSM_RESET_DONE_OUT => mgt_RX_FSM_RESET_DONE(4*i+3),
101  GT3_DATA_VALID_IN => mgt_DATA_VALID_IN (4*i+3),
102 
103  GT0_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i),
104  GT0_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i),
105  GT1_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i+1),
106  GT1_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i+1),
107  GT2_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i+2),
108  GT2_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i+2),
109  GT3_TXUSRCLK_OUT => mgt_TXUSRCLK_OUT(4*i+3),
110  GT3_RXUSRCLK_OUT => mgt_RXUSRCLK_OUT(4*i+3),
111 
112  --_________________________________________________________________________
113  --GT0 (X0Y0)
114  --____________________________CHANNEL PORTS________________________________
115 
116  gt0_rxpd_in => gt_rxpd_array(i).gt0_rxpd,
117  gt0_txpd_in => gt_txpd_array(i).gt0_txpd,
118  gt0_rxdata_out => rxdata_quad_array (i).gt0_rxdata_out,
119  gt0_rxdisperr_out => rxdisperr_quad_array(i).gt0_rxdisperr,
120  gt0_rxnotintable_out => rxnotintable_quad_array(i).gt0_rxnotintable,
121  gt0_rxbyterealign_out => rxbyterealign_quad_array(i).gt0_rxbyterealign,
122  gt0_rxcommadet_out => rxcommadet_quad_array(i).gt0_rxcommadet,
123  gt0_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt0_rxbyteisaligned,
124  gt0_rxchariscomma_out => rxchariscomma_quad_array(i).gt0_rxchariscomma_out,
125  gt0_rxcharisk_out => rxcharisk_quad_array(i).gt0_rxcharisk_out,
126  gt0_rxresetdone_out => rxresetdone_quad_array(i).gt0_rxresetdone,
127  gt0_txdata_in => txdata_quad_array(i).gt0_txdata_in,
128  gt0_txresetdone_out => txresetdone_quad_array(i).gt0_txresetdone,
129  gt0_txcharisk_in => txcharisk_quad_array (i).gt0_txcharisk,
130  --GT1 (X0Y1)
131  --____________________________CHANNEL PORTS________________________________
132 
133  gt1_rxpd_in => gt_rxpd_array(i).gt1_rxpd,
134  gt1_txpd_in => gt_txpd_array(i).gt1_txpd,
135  gt1_rxdata_out => rxdata_quad_array (i).gt1_rxdata_out,
136  gt1_rxdisperr_out => rxdisperr_quad_array(i).gt1_rxdisperr,
137  gt1_rxnotintable_out => rxnotintable_quad_array(i).gt1_rxnotintable,
138  gt1_rxbyterealign_out => rxbyterealign_quad_array(i).gt1_rxbyterealign,
139  gt1_rxcommadet_out => rxcommadet_quad_array(i).gt1_rxcommadet,
140  gt1_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt1_rxbyteisaligned,
141  gt1_rxchariscomma_out => rxchariscomma_quad_array(i).gt1_rxchariscomma_out,
142  gt1_rxcharisk_out => rxcharisk_quad_array(i).gt1_rxcharisk_out,
143  gt1_rxresetdone_out => rxresetdone_quad_array(i).gt1_rxresetdone,
144  gt1_txdata_in => txdata_quad_array(i).gt1_txdata_in,
145  gt1_txresetdone_out => txresetdone_quad_array(i).gt1_txresetdone,
146  gt1_txcharisk_in => txcharisk_quad_array (i).gt1_txcharisk,
147 
148  --GT2 (X0Y2)
149  --____________________________CHANNEL PORTS________________________________
150 
151  gt2_rxpd_in => gt_rxpd_array(i).gt2_rxpd,
152  gt2_txpd_in => gt_txpd_array(i).gt2_txpd,
153  gt2_rxdata_out => rxdata_quad_array (i).gt2_rxdata_out,
154  gt2_rxdisperr_out => rxdisperr_quad_array(i).gt2_rxdisperr,
155  gt2_rxnotintable_out => rxnotintable_quad_array(i).gt2_rxnotintable,
156  gt2_rxbyterealign_out => rxbyterealign_quad_array(i).gt2_rxbyterealign,
157  gt2_rxcommadet_out => rxcommadet_quad_array(i).gt2_rxcommadet,
158  gt2_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt2_rxbyteisaligned,
159  gt2_rxchariscomma_out => rxchariscomma_quad_array(i).gt2_rxchariscomma_out,
160  gt2_rxcharisk_out => rxcharisk_quad_array(i).gt2_rxcharisk_out,
161  gt2_rxresetdone_out => rxresetdone_quad_array(i).gt2_rxresetdone,
162  gt2_txdata_in => txdata_quad_array(i).gt2_txdata_in,
163  gt2_txresetdone_out => txresetdone_quad_array(i).gt2_txresetdone,
164  gt2_txcharisk_in => txcharisk_quad_array (i).gt2_txcharisk,
165 
166 
167  --GT3 (X0Y3)
168  --____________________________CHANNEL PORTS________________________________
169 
170  gt3_rxpd_in => gt_rxpd_array(i).gt3_rxpd,
171  gt3_txpd_in => gt_txpd_array(i).gt3_txpd,
172  gt3_rxdata_out => rxdata_quad_array (i).gt3_rxdata_out,
173  gt3_rxdisperr_out => rxdisperr_quad_array(i).gt3_rxdisperr,
174  gt3_rxnotintable_out => rxnotintable_quad_array(i).gt3_rxnotintable,
175  gt3_rxbyterealign_out => rxbyterealign_quad_array(i).gt3_rxbyterealign,
176  gt3_rxcommadet_out => rxcommadet_quad_array(i).gt3_rxcommadet,
177  gt3_rxbyteisaligned_out => rxbyteisaligned_quad_array(i).gt3_rxbyteisaligned,
178  gt3_rxchariscomma_out => rxchariscomma_quad_array(i).gt3_rxchariscomma_out,
179  gt3_rxcharisk_out => rxcharisk_quad_array(i).gt3_rxcharisk_out,
180  gt3_rxresetdone_out => rxresetdone_quad_array(i).gt3_rxresetdone,
181  gt3_txdata_in => txdata_quad_array(i).gt3_txdata_in,
182  gt3_txresetdone_out => txresetdone_quad_array(i).gt3_txresetdone,
183  gt3_txcharisk_in => txcharisk_quad_array (i).gt3_txcharisk,
184 
185 
186  --____________________________COMMON PORTS________________________________
187  GT0_QPLLLOCK_OUT => mgt_QPLLLOCK_OUT(i), --.GT0_QPLLLOCK_OUT,
188  GT0_QPLLREFCLKLOST_OUT => mgt_QPLLREFCLKLOST_OUT(i), --.GT0_QPLLREFCLKLOST_OUT,
189  sysclk_in => TTC_CLK
190 
191  );
192 
193  end generate MGT_GEN;
194 
195 end Behavioral;
mgt11g2_tx_rx_cfpga_gen.Behavioral
MGT quad.
Definition: mgt11g2_tx_rx_cfgpa_gen.vhd:61
mgt11g2_tx_rx_cfpga_gen
MGT quad.
Definition: mgt11g2_tx_rx_cfgpa_gen.vhd:16
mgt11g2_tx_rx_cfpga_wrapper
mgt selection wrapper
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:19
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxdata_out
out gt1_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:127
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxbyteisaligned_out
out gt3_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:182
mgt11g2_tx_rx_cfpga_wrapper.gt2_txresetdone_out
out gt2_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:168
mgt11g2_tx_rx_cfpga_wrapper.GT3_DATA_VALID_IN
in GT3_DATA_VALID_IN std_logic
status o3f data valid gt
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:64
mgt11g2_tx_rx_cfpga_wrapper.Q1_CLK1_GTREFCLK_PAD_N_IN
in Q1_CLK1_GTREFCLK_PAD_N_IN std_logic
clock input to the quad
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:33
mgt11g2_tx_rx_cfpga_wrapper.gt1_txdata_in
in gt1_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:141
mgt11g2_tx_rx_cfpga_wrapper.GT0_TXUSRCLK_OUT
out GT0_TXUSRCLK_OUT std_logic
tx user clock out gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:66
mgt11g2_tx_rx_cfpga_wrapper.TXN_OUT
out TXN_OUT std_logic_vector( 3 downto 0)
tx quad output
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:39
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxdisperr_out
out gt0_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports -for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:104
mgt11g2_tx_rx_cfpga_wrapper.GT3_TX_FSM_RESET_DONE_OUT
out GT3_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:60
mgt11g2_tx_rx_cfpga_wrapper.GT2_RX_FSM_RESET_DONE_OUT
out GT2_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:56
mgt11g2_tx_rx_cfpga_wrapper.GT0_DATA_VALID_IN
in GT0_DATA_VALID_IN std_logic
status of data valid gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:46
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxresetdone_out
out gt2_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:164
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxpd_in
in gt2_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:149
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxdata_out
out gt0_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:102
mgt11g2_tx_rx_cfpga_wrapper.GT2_TXUSRCLK_OUT
out GT2_TXUSRCLK_OUT std_logic
tx user clock out gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:82
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxdisperr_out
out gt3_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:179
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxresetdone_out
out gt1_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:139
mgt11g2_tx_rx_cfpga_wrapper.gt0_txdata_in
in gt0_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:117
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxdata_out
out gt3_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:177
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxbyteisaligned_out
out gt2_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:157
mgt11g2_tx_rx_cfpga_wrapper.GT1_RX_FSM_RESET_DONE_OUT
out GT1_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:50
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxchariscomma_out
out gt0_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:112
mgt11g2_tx_rx_cfpga_wrapper.gt0_txresetdone_out
out gt0_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:119
mgt11g2_tx_rx_cfpga_wrapper.GT3_TXUSRCLK_OUT
out GT3_TXUSRCLK_OUT std_logic
tx user clock out gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:90
mgt11g2_tx_rx_cfpga_wrapper.GT3_RX_FSM_RESET_DONE_OUT
out GT3_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:62
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxdisperr_out
out gt2_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:154
mgt11g2_tx_rx_cfpga_wrapper.GT1_DATA_VALID_IN
in GT1_DATA_VALID_IN std_logic
status of data valid gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:52
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxresetdone_out
out gt0_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:115
mgt11g2_tx_rx_cfpga_wrapper.gt3_txdata_in
in gt3_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:191
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxresetdone_out
out gt3_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:189
mgt11g2_tx_rx_cfpga_wrapper.gt3_txcharisk_in
in gt3_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:195
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxpd_in
in gt0_rxpd_in std_logic_vector( 1 downto 0)
rx power down bit
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:98
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxchariscomma_out
out gt2_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:161
mgt11g2_tx_rx_cfpga_wrapper.GT3_RXUSRCLK_OUT
out GT3_RXUSRCLK_OUT std_logic
rx user clock out gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:94
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxbyteisaligned_out
out gt0_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:107
mgt11g2_tx_rx_cfpga_wrapper.GT0_TX_FSM_RESET_DONE_OUT
out GT0_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:42
mgt11g2_tx_rx_cfpga_wrapper.SOFT_RESET_TX_IN
in SOFT_RESET_TX_IN std_logic
soft reset of tx quad
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:29
mgt11g2_tx_rx_cfpga_wrapper.GT1_RXUSRCLK_OUT
out GT1_RXUSRCLK_OUT std_logic
rx user clock out gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:78
mgt11g2_tx_rx_cfpga_wrapper.gt1_txresetdone_out
out gt1_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:143
mgt11g2_tx_rx_cfpga_wrapper.gt1_txcharisk_in
in gt1_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:145
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxpd_in
in gt1_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:124
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxbyteisaligned_out
out gt1_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:132
mgt11g2_tx_rx_cfpga_wrapper.RXN_IN
in RXN_IN std_logic_vector( 3 downto 0)
rx quad input
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:36
mgt11g2_tx_rx_cfpga_wrapper.GT2_RXUSRCLK_OUT
out GT2_RXUSRCLK_OUT std_logic
rx user clock out gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:86
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxchariscomma_out
out gt1_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:136
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxdata_out
out gt2_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:152
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxpd_in
in gt3_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:174
mgt11g2_tx_rx_cfpga_wrapper.gt2_txcharisk_in
in gt2_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:170
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxchariscomma_out
out gt3_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:186
mgt11g2_tx_rx_cfpga_wrapper.gt2_txdata_in
in gt2_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:166
mgt11g2_tx_rx_cfpga_wrapper.GT2_TX_FSM_RESET_DONE_OUT
out GT2_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:54
mgt11g2_tx_rx_cfpga_wrapper.gt0_txpd_in
in gt0_txpd_in std_logic_vector( 1 downto 0)
tx power down bit
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:100
mgt11g2_tx_rx_cfpga_wrapper.gt0_txcharisk_in
in gt0_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:121
mgt11g2_tx_rx_cfpga_wrapper.GT0_RXUSRCLK_OUT
out GT0_RXUSRCLK_OUT std_logic
rx user clock out gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:70
mgt11g2_tx_rx_cfpga_wrapper.GT0_RX_FSM_RESET_DONE_OUT
out GT0_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gto
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:44
mgt11g2_tx_rx_cfpga_wrapper.GT2_DATA_VALID_IN
in GT2_DATA_VALID_IN std_logic
status of data valid gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:58
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxdisperr_out
out gt1_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:129
mgt11g2_tx_rx_cfpga_wrapper.gt3_txresetdone_out
out gt3_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:193
mgt11g2_tx_rx_cfpga_wrapper.SOFT_RESET_RX_IN
in SOFT_RESET_RX_IN std_logic
soft reset of rx quad
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:31
mgt11g2_tx_rx_cfpga_wrapper.GT1_TX_FSM_RESET_DONE_OUT
out GT1_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:48
mgt11g2_tx_rx_cfpga_wrapper.GT1_TXUSRCLK_OUT
out GT1_TXUSRCLK_OUT std_logic
tx user clock out gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:74
mgt_type
Definition: mgt_type_pkg.vhd:4
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