eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

Back to eFEX documentation
mgt11g2_tx_rx_cfgpa_wrapper.vhd
Go to the documentation of this file.
1 
7 
8 
9 
10 
11 library ieee;
12 use ieee.std_logic_1164.all;
13 use ieee.numeric_std.all;
14 library UNISIM;
15 use UNISIM.VCOMPONENTS.ALL;
16 
18 
19 entity mgt11g2_tx_rx_cfpga_wrapper is
20 
21 generic
22 (
23  -- Simulation attributes
24  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "FALSE"; -- Set to TRUE to speed up sim reset
25  STABLE_CLOCK_PERIOD : integer := 16
26 );
27 port
28 (
29  SOFT_RESET_TX_IN : in std_logic;
31  SOFT_RESET_RX_IN : in std_logic;
33  Q1_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
34  Q1_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
36  RXN_IN : in std_logic_vector(3 downto 0);
37  RXP_IN : in std_logic_vector(3 downto 0);
39  TXN_OUT : out std_logic_vector(3 downto 0);
40  TXP_OUT : out std_logic_vector(3 downto 0);
42  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
44  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
46  GT0_DATA_VALID_IN : in std_logic;
48  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
50  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
52  GT1_DATA_VALID_IN : in std_logic;
54  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
56  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
58  GT2_DATA_VALID_IN : in std_logic;
60  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
62  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
64  GT3_DATA_VALID_IN : in std_logic;
66  GT0_TXUSRCLK_OUT : out std_logic;
68  GT0_TXUSRCLK2_OUT : out std_logic;
70  GT0_RXUSRCLK_OUT : out std_logic;
72  GT0_RXUSRCLK2_OUT : out std_logic;
74  GT1_TXUSRCLK_OUT : out std_logic;
76  GT1_TXUSRCLK2_OUT : out std_logic;
78  GT1_RXUSRCLK_OUT : out std_logic;
80  GT1_RXUSRCLK2_OUT : out std_logic;
82  GT2_TXUSRCLK_OUT : out std_logic;
84  GT2_TXUSRCLK2_OUT : out std_logic;
86  GT2_RXUSRCLK_OUT : out std_logic;
88  GT2_RXUSRCLK2_OUT : out std_logic;
90  GT3_TXUSRCLK_OUT : out std_logic;
92  GT3_TXUSRCLK2_OUT : out std_logic;
94  GT3_RXUSRCLK_OUT : out std_logic;
96  GT3_RXUSRCLK2_OUT : out std_logic;
98  gt0_rxpd_in : in std_logic_vector(1 downto 0);
100  gt0_txpd_in : in std_logic_vector(1 downto 0);
102  gt0_rxdata_out : out std_logic_vector(31 downto 0);
104  gt0_rxdisperr_out : out std_logic_vector(3 downto 0);
105  gt0_rxnotintable_out : out std_logic_vector(3 downto 0);
107  gt0_rxbyteisaligned_out : out std_logic;
108  gt0_rxbyterealign_out : out std_logic;
109  gt0_rxcommadet_out : out std_logic;
110 
112  gt0_rxchariscomma_out : out std_logic_vector(3 downto 0);
113  gt0_rxcharisk_out : out std_logic_vector(3 downto 0);
115  gt0_rxresetdone_out : out std_logic;
117  gt0_txdata_in : in std_logic_vector(31 downto 0);
119  gt0_txresetdone_out : out std_logic;
121  gt0_txcharisk_in : in std_logic_vector(3 downto 0);
122  --GT1 (X1Y5)
124  gt1_rxpd_in : in std_logic_vector(1 downto 0);
125  gt1_txpd_in : in std_logic_vector(1 downto 0);
127  gt1_rxdata_out : out std_logic_vector(31 downto 0);
129  gt1_rxdisperr_out : out std_logic_vector(3 downto 0);
130  gt1_rxnotintable_out : out std_logic_vector(3 downto 0);
132  gt1_rxbyteisaligned_out : out std_logic;
133  gt1_rxbyterealign_out : out std_logic;
134  gt1_rxcommadet_out : out std_logic;
136  gt1_rxchariscomma_out : out std_logic_vector(3 downto 0);
137  gt1_rxcharisk_out : out std_logic_vector(3 downto 0);
139  gt1_rxresetdone_out : out std_logic;
141  gt1_txdata_in : in std_logic_vector(31 downto 0);
143  gt1_txresetdone_out : out std_logic;
145  gt1_txcharisk_in : in std_logic_vector(3 downto 0);
146  --_________________________________________________________________________
147  --GT2 (X1Y6)
149  gt2_rxpd_in : in std_logic_vector(1 downto 0);
150  gt2_txpd_in : in std_logic_vector(1 downto 0);
152  gt2_rxdata_out : out std_logic_vector(31 downto 0);
154  gt2_rxdisperr_out : out std_logic_vector(3 downto 0);
155  gt2_rxnotintable_out : out std_logic_vector(3 downto 0);
157  gt2_rxbyteisaligned_out : out std_logic;
158  gt2_rxbyterealign_out : out std_logic;
159  gt2_rxcommadet_out : out std_logic;
161  gt2_rxchariscomma_out : out std_logic_vector(3 downto 0);
162  gt2_rxcharisk_out : out std_logic_vector(3 downto 0);
164  gt2_rxresetdone_out : out std_logic;
166  gt2_txdata_in : in std_logic_vector(31 downto 0);
168  gt2_txresetdone_out : out std_logic;
170  gt2_txcharisk_in : in std_logic_vector(3 downto 0);
171  --_________________________________________________________________________
172  --GT3 (X1Y7)
174  gt3_rxpd_in : in std_logic_vector(1 downto 0);
175  gt3_txpd_in : in std_logic_vector(1 downto 0);
177  gt3_rxdata_out : out std_logic_vector(31 downto 0);
179  gt3_rxdisperr_out : out std_logic_vector(3 downto 0);
180  gt3_rxnotintable_out : out std_logic_vector(3 downto 0);
182  gt3_rxbyteisaligned_out : out std_logic;
183  gt3_rxbyterealign_out : out std_logic;
184  gt3_rxcommadet_out : out std_logic;
186  gt3_rxchariscomma_out : out std_logic_vector(3 downto 0);
187  gt3_rxcharisk_out : out std_logic_vector(3 downto 0);
189  gt3_rxresetdone_out : out std_logic;
191  gt3_txdata_in : in std_logic_vector(31 downto 0);
193  gt3_txresetdone_out : out std_logic;
195  gt3_txcharisk_in : in std_logic_vector(3 downto 0);
196 
197 
198  --____________________________COMMON PORTS________________________________
199  GT0_QPLLLOCK_OUT : out std_logic;
200  GT0_QPLLREFCLKLOST_OUT : out std_logic;
201  sysclk_in : in std_logic
202 );
203 end mgt11g2_tx_rx_cfpga_wrapper;
204 
206 
207 architecture RTL of mgt11g2_tx_rx_cfpga_wrapper is
208  attribute DowngradeIPIdentifiedWarnings: string;
209  attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
210 
211  attribute CORE_GENERATION_INFO : string;
212  attribute CORE_GENERATION_INFO of RTL : architecture is "mgt11g2_tx_rx_cfpga,gtwizard_v3_6_11,{protocol_file=Start_from_scratch}";
213 
214  --________________________________________________________________________
215  --GT0 (X1Y4)
216 
217  -------------------------- Channel - Clocking Ports ------------------------
218  signal gt0_gtnorthrefclk0_i : std_logic;
219  signal gt0_gtnorthrefclk1_i : std_logic;
220  signal gt0_gtsouthrefclk0_i : std_logic;
221  signal gt0_gtsouthrefclk1_i : std_logic;
222 
223  signal gt0_drpaddr_i : std_logic_vector(8 downto 0);
224  signal gt0_drpdi_i : std_logic_vector(15 downto 0);
225  signal gt0_drpdo_i : std_logic_vector(15 downto 0);
226  signal gt0_drpen_i : std_logic;
227  signal gt0_drprdy_i : std_logic;
228  signal gt0_drpwe_i : std_logic;
229  --________________________________________________________________________
230  --GT1 (X1Y5)
231  signal gt1_gtnorthrefclk0_i : std_logic;
232  signal gt1_gtnorthrefclk1_i : std_logic;
233  signal gt1_gtsouthrefclk0_i : std_logic;
234  signal gt1_gtsouthrefclk1_i : std_logic;
235 
236  signal gt1_drpaddr_i : std_logic_vector(8 downto 0);
237  signal gt1_drpdi_i : std_logic_vector(15 downto 0);
238  signal gt1_drpdo_i : std_logic_vector(15 downto 0);
239  signal gt1_drpen_i : std_logic;
240  signal gt1_drprdy_i : std_logic;
241  signal gt1_drpwe_i : std_logic;
242 
243  --_______________________________________________________________________
244  --GT2 (X1Y6)
245  signal gt2_gtnorthrefclk0_i : std_logic;
246  signal gt2_gtnorthrefclk1_i : std_logic;
247  signal gt2_gtsouthrefclk0_i : std_logic;
248  signal gt2_gtsouthrefclk1_i : std_logic;
249 
250  signal gt2_drpaddr_i : std_logic_vector(8 downto 0);
251  signal gt2_drpdi_i : std_logic_vector(15 downto 0);
252  signal gt2_drpdo_i : std_logic_vector(15 downto 0);
253  signal gt2_drpen_i : std_logic;
254  signal gt2_drprdy_i : std_logic;
255  signal gt2_drpwe_i : std_logic;
256 
257  --________________________________________________________________________
258  --GT3 (X1Y7)
259  signal gt3_gtnorthrefclk0_i : std_logic;
260  signal gt3_gtnorthrefclk1_i : std_logic;
261  signal gt3_gtsouthrefclk0_i : std_logic;
262  signal gt3_gtsouthrefclk1_i : std_logic;
263 
264  signal gt3_drpaddr_i : std_logic_vector(8 downto 0);
265  signal gt3_drpdi_i : std_logic_vector(15 downto 0);
266  signal gt3_drpdo_i : std_logic_vector(15 downto 0);
267  signal gt3_drpen_i : std_logic;
268  signal gt3_drprdy_i : std_logic;
269  signal gt3_drpwe_i : std_logic;
270 
271  signal tied_to_ground_i : std_logic;
272  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
273  signal tied_to_vcc_i : std_logic;
274  signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
275 
276 
277 
278 
279 
280 
281  -- ************************** Main Body of Code *******************************
282 begin
283 
284  -- Static signal Assignment
285  tied_to_ground_i <= '0';
286  tied_to_ground_vec_i <= x"0000000000000000";
287  tied_to_vcc_i <= '1';
288  tied_to_vcc_vec_i <= "11111111";
289 
290 
291  --q1_clk1_refclk_i <= '0';
292  gt0_gtnorthrefclk0_i <= tied_to_ground_i;
293  gt0_gtnorthrefclk1_i <= tied_to_ground_i;
294  gt0_gtsouthrefclk0_i <= tied_to_ground_i;
295  gt0_gtsouthrefclk1_i <= tied_to_ground_i;
296  gt1_gtnorthrefclk0_i <= tied_to_ground_i;
297  gt1_gtnorthrefclk1_i <= tied_to_ground_i;
298  gt1_gtsouthrefclk0_i <= tied_to_ground_i;
299  gt1_gtsouthrefclk1_i <= tied_to_ground_i;
300  gt2_gtnorthrefclk0_i <= tied_to_ground_i;
301  gt2_gtnorthrefclk1_i <= tied_to_ground_i;
302  gt2_gtsouthrefclk0_i <= tied_to_ground_i;
303  gt2_gtsouthrefclk1_i <= tied_to_ground_i;
304  gt3_gtnorthrefclk0_i <= tied_to_ground_i;
305  gt3_gtnorthrefclk1_i <= tied_to_ground_i;
306  gt3_gtsouthrefclk0_i <= tied_to_ground_i;
307  gt3_gtsouthrefclk1_i <= tied_to_ground_i;
308  ----------------------------- The GT Wrapper -----------------------------
309 
310 
311 
312  mgt11g2_tx_rx_cfpga_support_i : entity work.mgt11g2_tx_rx_cfpga_support
313  generic map
314  (
315  EXAMPLE_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
316  STABLE_CLOCK_PERIOD => STABLE_CLOCK_PERIOD
317  )
318  port map
319  (
320  SOFT_RESET_TX_IN => SOFT_RESET_TX_IN ,
321  SOFT_RESET_RX_IN => SOFT_RESET_RX_IN ,
322  DONT_RESET_ON_DATA_ERROR_IN => tied_to_ground_i ,
323  Q1_CLK1_GTREFCLK_PAD_N_IN => Q1_CLK1_GTREFCLK_PAD_N_IN,
324  Q1_CLK1_GTREFCLK_PAD_P_IN => Q1_CLK1_GTREFCLK_PAD_P_IN,
325 
326  GT0_TX_FSM_RESET_DONE_OUT => GT0_TX_FSM_RESET_DONE_OUT,
327  GT0_RX_FSM_RESET_DONE_OUT => GT0_RX_FSM_RESET_DONE_OUT,
328  GT0_DATA_VALID_IN => GT0_DATA_VALID_IN,
329  GT1_TX_FSM_RESET_DONE_OUT => GT1_TX_FSM_RESET_DONE_OUT,
330  GT1_RX_FSM_RESET_DONE_OUT => GT1_RX_FSM_RESET_DONE_OUT,
331  GT1_DATA_VALID_IN => GT1_DATA_VALID_IN,
332  GT2_TX_FSM_RESET_DONE_OUT => GT2_TX_FSM_RESET_DONE_OUT,
333  GT2_RX_FSM_RESET_DONE_OUT => GT2_RX_FSM_RESET_DONE_OUT,
334  GT2_DATA_VALID_IN => GT2_DATA_VALID_IN ,
335  GT3_TX_FSM_RESET_DONE_OUT => GT3_TX_FSM_RESET_DONE_OUT,
336  GT3_RX_FSM_RESET_DONE_OUT => GT3_RX_FSM_RESET_DONE_OUT,
337  GT3_DATA_VALID_IN => GT3_DATA_VALID_IN,
338 
339  GT0_TXUSRCLK_OUT => gt0_txusrclk_out,
340  GT0_TXUSRCLK2_OUT => open,
341  GT0_RXUSRCLK_OUT => gt0_rxusrclk_out,
342  GT0_RXUSRCLK2_OUT => open,
343 
344  GT1_TXUSRCLK_OUT => gt1_txusrclk_out,
345  GT1_TXUSRCLK2_OUT => open,
346  GT1_RXUSRCLK_OUT => gt1_rxusrclk_out,
347  GT1_RXUSRCLK2_OUT => open,
348 
349  GT2_TXUSRCLK_OUT => gt2_txusrclk_out,
350  GT2_TXUSRCLK2_OUT => open,
351  GT2_RXUSRCLK_OUT => gt2_rxusrclk_out,
352  GT2_RXUSRCLK2_OUT => open,
353 
354  GT3_TXUSRCLK_OUT => gt3_txusrclk_out,
355  GT3_TXUSRCLK2_OUT => open,
356  GT3_RXUSRCLK_OUT => gt3_rxusrclk_out,
357  GT3_RXUSRCLK2_OUT => open,
358 
359 
360  --_____________________________________________________________________
361  --_____________________________________________________________________
362  --GT0 (X1Y4)
363 
364  -------------------------- Channel - Clocking Ports ------------------------
365  gt0_gtnorthrefclk0_in => gt0_gtnorthrefclk0_i,
366  gt0_gtnorthrefclk1_in => gt0_gtnorthrefclk1_i,
367  gt0_gtsouthrefclk0_in => gt0_gtsouthrefclk0_i,
368  gt0_gtsouthrefclk1_in => gt0_gtsouthrefclk1_i,
369 
370  ---------------------------- Channel - DRP Ports --------------------------
371  gt0_drpaddr_in => gt0_drpaddr_i,
372  gt0_drpdi_in => gt0_drpdi_i,
373  gt0_drpdo_out => gt0_drpdo_i,
374  gt0_drpen_in => gt0_drpen_i,
375  gt0_drprdy_out => gt0_drprdy_i,
376  gt0_drpwe_in => gt0_drpwe_i,
377  ------------------------------ Power-Down Ports ----------------------------
378  gt0_rxpd_in => gt0_rxpd_in,
379  gt0_txpd_in => gt0_txpd_in,
380  --------------------- RX Initialization and Reset Ports --------------------
381  gt0_eyescanreset_in => tied_to_ground_i,
382  gt0_rxuserrdy_in => tied_to_ground_i, --tied_to_vcc_i,
383  -------------------------- RX Margin Analysis Ports ------------------------
384  gt0_eyescandataerror_out => open,
385  gt0_eyescantrigger_in => tied_to_ground_i,
386  ------------------- Receive Ports - Digital Monitor Ports ------------------
387  gt0_dmonitorout_out => open,
388  ------------------ Receive Ports - FPGA RX interface Ports -----------------
389  gt0_rxdata_out => gt0_rxdata_out,
390  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
391  gt0_rxdisperr_out => gt0_rxdisperr_out,
392  gt0_rxnotintable_out => gt0_rxnotintable_out,
393  ------------------------ Receive Ports - RX AFE Ports ----------------------
394  gt0_gthrxn_in => RXN_IN(0),
395  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
396  gt0_rxphmonitor_out => open,
397  gt0_rxphslipmonitor_out => open,
398  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
399  gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
400  gt0_rxbyterealign_out => gt0_rxbyterealign_out,
401  gt0_rxcommadet_out => gt0_rxcommadet_out,
402  --------------------- Receive Ports - RX Equalizer Ports -------------------
403  gt0_rxmonitorout_out => open,
404  gt0_rxmonitorsel_in => "00",
405  --------------- Receive Ports - RX Fabric Output Control Ports -------------
406  gt0_rxoutclkfabric_out => open,
407  ------------- Receive Ports - RX Initialization and Reset Ports ------------
408  gt0_gtrxreset_in => tied_to_ground_i,
409  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
410  gt0_rxchariscomma_out => gt0_rxchariscomma_out,
411  gt0_rxcharisk_out => gt0_rxcharisk_out,
412  ------------------------ Receive Ports -RX AFE Ports -----------------------
413  gt0_gthrxp_in => RXP_IN(0),
414  -------------- Receive Ports -RX Initialization and Reset Ports ------------
415  gt0_rxresetdone_out => gt0_rxresetdone_out,
416  --------------------- TX Initialization and Reset Ports --------------------
417  gt0_gttxreset_in => tied_to_ground_i,
418  gt0_txuserrdy_in => tied_to_ground_i, --tied_to_vcc_i,
419  ------------------ Transmit Ports - TX Data Path interface -----------------
420  gt0_txdata_in => gt0_txdata_in,
421  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
422  gt0_gthtxn_out => TXN_OUT(0),
423  gt0_gthtxp_out => TXP_OUT(0),
424  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
425  gt0_txoutclkfabric_out => open,
426  gt0_txoutclkpcs_out => open,
427  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
428  gt0_txresetdone_out => gt0_txresetdone_out,
429  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
430  gt0_txcharisk_in => gt0_txcharisk_in,
431 
432 
433 
434  --_____________________________________________________________________
435  --_____________________________________________________________________
436  --GT1 (X1Y5)
437 
438  -------------------------- Channel - Clocking Ports ------------------------
439  gt1_gtnorthrefclk0_in => gt1_gtnorthrefclk0_i,
440  gt1_gtnorthrefclk1_in => gt1_gtnorthrefclk1_i,
441  gt1_gtsouthrefclk0_in => gt1_gtsouthrefclk0_i,
442  gt1_gtsouthrefclk1_in => gt1_gtsouthrefclk1_i,
443  ---------------------------- Channel - DRP Ports --------------------------
444  gt1_drpaddr_in => gt1_drpaddr_i,
445  gt1_drpdi_in => gt1_drpdi_i,
446  gt1_drpdo_out => gt1_drpdo_i,
447  gt1_drpen_in => gt1_drpen_i,
448  gt1_drprdy_out => gt1_drprdy_i,
449  gt1_drpwe_in => gt1_drpwe_i,
450  ------------------------------ Power-Down Ports ----------------------------
451  gt1_rxpd_in => gt1_rxpd_in,
452  gt1_txpd_in => gt1_txpd_in,
453  --------------------- RX Initialization and Reset Ports --------------------
454  gt1_eyescanreset_in => tied_to_ground_i,
455  gt1_rxuserrdy_in => tied_to_ground_i, --tied_to_vcc_i,
456  -------------------------- RX Margin Analysis Ports ------------------------
457  gt1_eyescandataerror_out => open,
458  gt1_eyescantrigger_in => tied_to_ground_i,
459  ------------------- Receive Ports - Digital Monitor Ports ------------------
460  gt1_dmonitorout_out => open,
461  ------------------ Receive Ports - FPGA RX interface Ports -----------------
462  gt1_rxdata_out => gt1_rxdata_out,
463  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
464  gt1_rxdisperr_out => gt1_rxdisperr_out,
465  gt1_rxnotintable_out => gt1_rxnotintable_out,
466  ------------------------ Receive Ports - RX AFE Ports ----------------------
467  gt1_gthrxn_in => RXN_IN(1),
468  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
469  gt1_rxphmonitor_out => open,
470  gt1_rxphslipmonitor_out => open,
471  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
472  gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
473  gt1_rxbyterealign_out => gt1_rxbyterealign_out,
474  gt1_rxcommadet_out => gt1_rxcommadet_out,
475  --------------------- Receive Ports - RX Equalizer Ports -------------------
476  gt1_rxmonitorout_out => open,
477  gt1_rxmonitorsel_in => "00",
478  --------------- Receive Ports - RX Fabric Output Control Ports -------------
479  gt1_rxoutclkfabric_out => open,
480  ------------- Receive Ports - RX Initialization and Reset Ports ------------
481  gt1_gtrxreset_in => tied_to_ground_i,
482  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
483  gt1_rxchariscomma_out => gt1_rxchariscomma_out,
484  gt1_rxcharisk_out => gt1_rxcharisk_out,
485  ------------------------ Receive Ports -RX AFE Ports -----------------------
486  gt1_gthrxp_in => RXP_IN(1),
487  -------------- Receive Ports -RX Initialization and Reset Ports ------------
488  gt1_rxresetdone_out => gt1_rxresetdone_out,
489  --------------------- TX Initialization and Reset Ports --------------------
490  gt1_gttxreset_in => tied_to_ground_i,
491  gt1_txuserrdy_in => tied_to_ground_i, --tied_to_vcc_i,
492  ------------------ Transmit Ports - TX Data Path interface -----------------
493  gt1_txdata_in => gt1_txdata_in,
494  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
495  gt1_gthtxn_out => TXN_OUT(1),
496  gt1_gthtxp_out => TXP_OUT(1),
497  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
498  gt1_txoutclkfabric_out => open,
499  gt1_txoutclkpcs_out => open,
500  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
501  gt1_txresetdone_out => gt1_txresetdone_out,
502  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
503  gt1_txcharisk_in => gt1_txcharisk_in,
504 
505 
506 
507  --_____________________________________________________________________
508  --_____________________________________________________________________
509  --GT2 (X1Y6)
510 
511  -------------------------- Channel - Clocking Ports ------------------------
512  gt2_gtnorthrefclk0_in => gt2_gtnorthrefclk0_i,
513  gt2_gtnorthrefclk1_in => gt2_gtnorthrefclk1_i,
514  gt2_gtsouthrefclk0_in => gt2_gtsouthrefclk0_i,
515  gt2_gtsouthrefclk1_in => gt2_gtsouthrefclk1_i,
516  ---------------------------- Channel - DRP Ports --------------------------
517  gt2_drpaddr_in => gt2_drpaddr_i,
518  gt2_drpdi_in => gt2_drpdi_i,
519  gt2_drpdo_out => gt2_drpdo_i,
520  gt2_drpen_in => gt2_drpen_i,
521  gt2_drprdy_out => gt2_drprdy_i,
522  gt2_drpwe_in => gt2_drpwe_i,
523 
524  ------------------------------ Power-Down Ports ----------------------------
525  gt2_rxpd_in => gt2_rxpd_in,
526  gt2_txpd_in => gt2_txpd_in,
527  --------------------- RX Initialization and Reset Ports --------------------
528  gt2_eyescanreset_in => tied_to_ground_i,
529  gt2_rxuserrdy_in => tied_to_ground_i, --tied_to_vcc_i,
530  -------------------------- RX Margin Analysis Ports ------------------------
531  gt2_eyescandataerror_out => open,
532  gt2_eyescantrigger_in => tied_to_ground_i,
533  ------------------- Receive Ports - Digital Monitor Ports ------------------
534  gt2_dmonitorout_out => open,
535  ------------------ Receive Ports - FPGA RX interface Ports -----------------
536  gt2_rxdata_out => gt2_rxdata_out,
537  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
538  gt2_rxdisperr_out => gt2_rxdisperr_out,
539  gt2_rxnotintable_out => gt2_rxnotintable_out,
540  ------------------------ Receive Ports - RX AFE Ports ----------------------
541  gt2_gthrxn_in => RXN_IN(2),
542  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
543  gt2_rxphmonitor_out => open,
544  gt2_rxphslipmonitor_out => open,
545  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
546  gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
547  gt2_rxbyterealign_out => gt2_rxbyterealign_out,
548  gt2_rxcommadet_out => gt2_rxcommadet_out,
549  --------------------- Receive Ports - RX Equalizer Ports -------------------
550  gt2_rxmonitorout_out => open,
551  gt2_rxmonitorsel_in => "00",
552  --------------- Receive Ports - RX Fabric Output Control Ports -------------
553  gt2_rxoutclkfabric_out => open,
554  ------------- Receive Ports - RX Initialization and Reset Ports ------------
555  gt2_gtrxreset_in => tied_to_ground_i,
556  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
557  gt2_rxchariscomma_out => gt2_rxchariscomma_out,
558  gt2_rxcharisk_out => gt2_rxcharisk_out,
559  ------------------------ Receive Ports -RX AFE Ports -----------------------
560  gt2_gthrxp_in => RXP_IN(2),
561  -------------- Receive Ports -RX Initialization and Reset Ports ------------
562  gt2_rxresetdone_out => gt2_rxresetdone_out,
563  --------------------- TX Initialization and Reset Ports --------------------
564  gt2_gttxreset_in => tied_to_ground_i,
565  gt2_txuserrdy_in => tied_to_ground_i, --tied_to_vcc_i,
566  ------------------ Transmit Ports - TX Data Path interface -----------------
567  gt2_txdata_in => gt2_txdata_in,
568  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
569  gt2_gthtxn_out => TXN_OUT(2),
570  gt2_gthtxp_out => TXP_OUT(2),
571  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
572  gt2_txoutclkfabric_out => open,
573  gt2_txoutclkpcs_out => open,
574  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
575  gt2_txresetdone_out => gt2_txresetdone_out,
576  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
577  gt2_txcharisk_in => gt2_txcharisk_in,
578 
579 
580 
581  --_____________________________________________________________________
582  --_____________________________________________________________________
583  --GT3 (X1Y7)
584 
585  -------------------------- Channel - Clocking Ports ------------------------
586  gt3_gtnorthrefclk0_in => gt3_gtnorthrefclk0_i,
587  gt3_gtnorthrefclk1_in => gt3_gtnorthrefclk1_i,
588  gt3_gtsouthrefclk0_in => gt3_gtsouthrefclk0_i,
589  gt3_gtsouthrefclk1_in => gt3_gtsouthrefclk1_i,
590 
591  ---------------------------- Channel - DRP Ports --------------------------
592  gt3_drpaddr_in => gt3_drpaddr_i,
593  gt3_drpdi_in => gt3_drpdi_i,
594  gt3_drpdo_out => gt3_drpdo_i,
595  gt3_drpen_in => gt3_drpen_i,
596  gt3_drprdy_out => gt3_drprdy_i,
597  gt3_drpwe_in => gt3_drpwe_i,
598 
599  ------------------------------ Power-Down Ports ----------------------------
600  gt3_rxpd_in => gt3_rxpd_in,
601  gt3_txpd_in => gt3_txpd_in,
602  --------------------- RX Initialization and Reset Ports --------------------
603  gt3_eyescanreset_in => tied_to_ground_i,
604  gt3_rxuserrdy_in => tied_to_ground_i, -- tied_to_vcc_i,
605  -------------------------- RX Margin Analysis Ports ------------------------
606  gt3_eyescandataerror_out => open,
607  gt3_eyescantrigger_in => tied_to_ground_i,
608  ------------------- Receive Ports - Digital Monitor Ports ------------------
609  gt3_dmonitorout_out => open,
610  ------------------ Receive Ports - FPGA RX interface Ports -----------------
611  gt3_rxdata_out => gt3_rxdata_out,
612  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
613  gt3_rxdisperr_out => gt3_rxdisperr_out,
614  gt3_rxnotintable_out => gt3_rxnotintable_out,
615  ------------------------ Receive Ports - RX AFE Ports ----------------------
616  gt3_gthrxn_in => RXN_IN(3),
617  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
618  gt3_rxphmonitor_out => open,
619  gt3_rxphslipmonitor_out => open,
620  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
621  gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
622  gt3_rxbyterealign_out => gt3_rxbyterealign_out,
623  gt3_rxcommadet_out => gt3_rxcommadet_out,
624  --------------------- Receive Ports - RX Equalizer Ports -------------------
625  gt3_rxmonitorout_out => open,
626  gt3_rxmonitorsel_in => "00",
627  --------------- Receive Ports - RX Fabric Output Control Ports -------------
628  gt3_rxoutclkfabric_out => open,
629  ------------- Receive Ports - RX Initialization and Reset Ports ------------
630  gt3_gtrxreset_in => tied_to_ground_i,
631  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
632  gt3_rxchariscomma_out => gt3_rxchariscomma_out,
633  gt3_rxcharisk_out => gt3_rxcharisk_out,
634  ------------------------ Receive Ports -RX AFE Ports -----------------------
635  gt3_gthrxp_in => RXP_IN(3),
636  -------------- Receive Ports -RX Initialization and Reset Ports ------------
637  gt3_rxresetdone_out => gt3_rxresetdone_out,
638  --------------------- TX Initialization and Reset Ports --------------------
639  gt3_gttxreset_in => tied_to_ground_i,
640  gt3_txuserrdy_in => tied_to_ground_i, --tied_to_vcc_i,
641  ------------------ Transmit Ports - TX Data Path interface -----------------
642  gt3_txdata_in => gt3_txdata_in,
643  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
644  gt3_gthtxn_out => TXN_OUT(3),
645  gt3_gthtxp_out => TXP_OUT(3),
646  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
647  gt3_txoutclkfabric_out => open,
648  gt3_txoutclkpcs_out => open,
649  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
650  gt3_txresetdone_out => gt3_txresetdone_out,
651  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
652  gt3_txcharisk_in => gt3_txcharisk_in,
653 
654 
655 
656  --____________________________COMMON PORTS________________________________
657  GT0_QPLLLOCK_OUT => GT0_QPLLLOCK_OUT,
658  GT0_QPLLREFCLKLOST_OUT => GT0_QPLLREFCLKLOST_OUT,
659  GT0_QPLLOUTCLK_OUT => open,
660  GT0_QPLLOUTREFCLK_OUT => open,
661  sysclk_in => sysclk_in
662  );
663 
664 
665  gt0_drpaddr_i <= (others => '0');
666  gt0_drpdi_i <= (others => '0');
667  gt0_drpen_i <= '0';
668  gt0_drpwe_i <= '0';
669  gt1_drpaddr_i <= (others => '0');
670  gt1_drpdi_i <= (others => '0');
671  gt1_drpen_i <= '0';
672  gt1_drpwe_i <= '0';
673  gt2_drpaddr_i <= (others => '0');
674  gt2_drpdi_i <= (others => '0');
675  gt2_drpen_i <= '0';
676  gt2_drpwe_i <= '0';
677  gt3_drpaddr_i <= (others => '0');
678  gt3_drpdi_i <= (others => '0');
679  gt3_drpen_i <= '0';
680  gt3_drpwe_i <= '0';
681 
682 
683 end RTL;
684 
685 
mgt11g2_tx_rx_cfpga_support
Definition: mgt11g2_tx_rx_cfpga_support.vhd:74
mgt11g2_tx_rx_cfpga_wrapper.RTL
mgt selection wrapper
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:207
mgt11g2_tx_rx_cfpga_wrapper
mgt selection wrapper
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:19
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxdata_out
out gt1_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:127
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxbyteisaligned_out
out gt3_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:182
mgt11g2_tx_rx_cfpga_wrapper.gt2_txresetdone_out
out gt2_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:168
mgt11g2_tx_rx_cfpga_wrapper.GT3_DATA_VALID_IN
in GT3_DATA_VALID_IN std_logic
status o3f data valid gt
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:64
mgt11g2_tx_rx_cfpga_wrapper.GT0_TXUSRCLK2_OUT
out GT0_TXUSRCLK2_OUT std_logic
GT0_TXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:68
mgt11g2_tx_rx_cfpga_wrapper.Q1_CLK1_GTREFCLK_PAD_N_IN
in Q1_CLK1_GTREFCLK_PAD_N_IN std_logic
clock input to the quad
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:33
mgt11g2_tx_rx_cfpga_wrapper.gt1_txdata_in
in gt1_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:141
mgt11g2_tx_rx_cfpga_wrapper.GT0_TXUSRCLK_OUT
out GT0_TXUSRCLK_OUT std_logic
tx user clock out gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:66
mgt11g2_tx_rx_cfpga_wrapper.TXN_OUT
out TXN_OUT std_logic_vector( 3 downto 0)
tx quad output
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:39
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxdisperr_out
out gt0_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports -for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:104
mgt11g2_tx_rx_cfpga_wrapper.GT3_TX_FSM_RESET_DONE_OUT
out GT3_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:60
mgt11g2_tx_rx_cfpga_wrapper.GT2_RX_FSM_RESET_DONE_OUT
out GT2_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:56
mgt11g2_tx_rx_cfpga_wrapper.GT0_DATA_VALID_IN
in GT0_DATA_VALID_IN std_logic
status of data valid gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:46
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxresetdone_out
out gt2_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:164
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxpd_in
in gt2_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:149
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxdata_out
out gt0_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:102
mgt11g2_tx_rx_cfpga_wrapper.GT2_TXUSRCLK_OUT
out GT2_TXUSRCLK_OUT std_logic
tx user clock out gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:82
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxdisperr_out
out gt3_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:179
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxresetdone_out
out gt1_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:139
mgt11g2_tx_rx_cfpga_wrapper.gt0_txdata_in
in gt0_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:117
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxdata_out
out gt3_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:177
mgt11g2_tx_rx_cfpga_wrapper.GT1_RXUSRCLK2_OUT
out GT1_RXUSRCLK2_OUT std_logic
GT1_RXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:80
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxbyteisaligned_out
out gt2_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:157
mgt11g2_tx_rx_cfpga_wrapper.GT2_TXUSRCLK2_OUT
out GT2_TXUSRCLK2_OUT std_logic
GT2_TXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:84
mgt11g2_tx_rx_cfpga_wrapper.GT1_RX_FSM_RESET_DONE_OUT
out GT1_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:50
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxchariscomma_out
out gt0_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:112
mgt11g2_tx_rx_cfpga_wrapper.gt0_txresetdone_out
out gt0_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:119
mgt11g2_tx_rx_cfpga_wrapper.GT3_TXUSRCLK_OUT
out GT3_TXUSRCLK_OUT std_logic
tx user clock out gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:90
mgt11g2_tx_rx_cfpga_wrapper.GT3_RX_FSM_RESET_DONE_OUT
out GT3_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:62
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxdisperr_out
out gt2_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:154
mgt11g2_tx_rx_cfpga_wrapper.GT1_DATA_VALID_IN
in GT1_DATA_VALID_IN std_logic
status of data valid gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:52
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxresetdone_out
out gt0_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:115
mgt11g2_tx_rx_cfpga_wrapper.gt3_txdata_in
in gt3_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:191
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxresetdone_out
out gt3_rxresetdone_out std_logic
Receive Ports -RX Initialization and Reset Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:189
mgt11g2_tx_rx_cfpga_wrapper.gt3_txcharisk_in
in gt3_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:195
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxpd_in
in gt0_rxpd_in std_logic_vector( 1 downto 0)
rx power down bit
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:98
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxchariscomma_out
out gt2_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:161
mgt11g2_tx_rx_cfpga_wrapper.GT3_RXUSRCLK_OUT
out GT3_RXUSRCLK_OUT std_logic
rx user clock out gt3
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:94
mgt11g2_tx_rx_cfpga_wrapper.gt0_rxbyteisaligned_out
out gt0_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:107
mgt11g2_tx_rx_cfpga_wrapper.GT0_TX_FSM_RESET_DONE_OUT
out GT0_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:42
mgt11g2_tx_rx_cfpga_wrapper.SOFT_RESET_TX_IN
in SOFT_RESET_TX_IN std_logic
soft reset of tx quad
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:29
mgt11g2_tx_rx_cfpga_wrapper.GT1_RXUSRCLK_OUT
out GT1_RXUSRCLK_OUT std_logic
rx user clock out gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:78
mgt11g2_tx_rx_cfpga_wrapper.gt1_txresetdone_out
out gt1_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:143
mgt11g2_tx_rx_cfpga_wrapper.GT3_RXUSRCLK2_OUT
out GT3_RXUSRCLK2_OUT std_logic
GT3_RXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:96
mgt11g2_tx_rx_cfpga_wrapper.gt1_txcharisk_in
in gt1_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:145
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxpd_in
in gt1_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:124
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxbyteisaligned_out
out gt1_rxbyteisaligned_out std_logic
Receive Ports - RX Byte and Word Alignment Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:132
mgt11g2_tx_rx_cfpga_wrapper.GT2_RXUSRCLK2_OUT
out GT2_RXUSRCLK2_OUT std_logic
GT2_RXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:88
mgt11g2_tx_rx_cfpga_wrapper.RXN_IN
in RXN_IN std_logic_vector( 3 downto 0)
rx quad input
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:36
mgt11g2_tx_rx_cfpga_wrapper.GT2_RXUSRCLK_OUT
out GT2_RXUSRCLK_OUT std_logic
rx user clock out gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:86
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxchariscomma_out
out gt1_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:136
mgt11g2_tx_rx_cfpga_wrapper.gt2_rxdata_out
out gt2_rxdata_out std_logic_vector( 31 downto 0)
Receive Ports - FPGA RX interface Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:152
mgt11g2_tx_rx_cfpga_wrapper.GT1_TXUSRCLK2_OUT
out GT1_TXUSRCLK2_OUT std_logic
GT1_TXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:76
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxpd_in
in gt3_rxpd_in std_logic_vector( 1 downto 0)
Power-Down Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:174
mgt11g2_tx_rx_cfpga_wrapper.gt2_txcharisk_in
in gt2_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:170
mgt11g2_tx_rx_cfpga_wrapper.gt3_rxchariscomma_out
out gt3_rxchariscomma_out std_logic_vector( 3 downto 0)
Receive Ports - RX8B/10B Decoder Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:186
mgt11g2_tx_rx_cfpga_wrapper.gt2_txdata_in
in gt2_txdata_in std_logic_vector( 31 downto 0)
Transmit Ports - TX Data Path interface for gt2.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:166
mgt11g2_tx_rx_cfpga_wrapper.GT2_TX_FSM_RESET_DONE_OUT
out GT2_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:54
mgt11g2_tx_rx_cfpga_wrapper.GT0_RXUSRCLK2_OUT
out GT0_RXUSRCLK2_OUT std_logic
GT0_RXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:72
mgt11g2_tx_rx_cfpga_wrapper.GT3_TXUSRCLK2_OUT
out GT3_TXUSRCLK2_OUT std_logic
GT3_TXUSRCLK2_OUT.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:92
mgt11g2_tx_rx_cfpga_wrapper.gt0_txpd_in
in gt0_txpd_in std_logic_vector( 1 downto 0)
tx power down bit
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:100
mgt11g2_tx_rx_cfpga_wrapper.gt0_txcharisk_in
in gt0_txcharisk_in std_logic_vector( 3 downto 0)
Transmit Transmit Ports - 8b10b Encoder Control Ports for gt0.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:121
mgt11g2_tx_rx_cfpga_wrapper.GT0_RXUSRCLK_OUT
out GT0_RXUSRCLK_OUT std_logic
rx user clock out gt0
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:70
mgt11g2_tx_rx_cfpga_wrapper.GT0_RX_FSM_RESET_DONE_OUT
out GT0_RX_FSM_RESET_DONE_OUT std_logic
status reset of the rx fsm gto
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:44
mgt11g2_tx_rx_cfpga_wrapper.GT2_DATA_VALID_IN
in GT2_DATA_VALID_IN std_logic
status of data valid gt2
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:58
mgt11g2_tx_rx_cfpga_wrapper.gt1_rxdisperr_out
out gt1_rxdisperr_out std_logic_vector( 3 downto 0)
Receive Ports - RX 8B/10B Decoder Ports for gt1.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:129
mgt11g2_tx_rx_cfpga_wrapper.gt3_txresetdone_out
out gt3_txresetdone_out std_logic
Transmit Ports - TX Initialization and Reset Ports for gt3.
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:193
mgt11g2_tx_rx_cfpga_wrapper.SOFT_RESET_RX_IN
in SOFT_RESET_RX_IN std_logic
soft reset of rx quad
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:31
mgt11g2_tx_rx_cfpga_wrapper.GT1_TX_FSM_RESET_DONE_OUT
out GT1_TX_FSM_RESET_DONE_OUT std_logic
status reset of the tx fsm gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:48
mgt11g2_tx_rx_cfpga_wrapper.GT1_TXUSRCLK_OUT
out GT1_TXUSRCLK_OUT std_logic
tx user clock out gt1
Definition: mgt11g2_tx_rx_cfgpa_wrapper.vhd:74
Generated on Tue Nov 11 2025 09:44:32 for eFEX firmware by   doxygen 1.9.1