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mgt11g2_tx_rx_cfpga_support.vhd
1 ------------------------------------------------------------------------------
2 -- ____ ____
3 -- / /\/ /
4 -- /___/ \ / Vendor: Xilinx
5 -- \ \ \/ Version : 3.6
6 -- \ \ Application : 7 Series FPGAs Transceivers Wizard
7 -- / / Filename : mgt11g2_tx_rx_cfpga_support.vhd
8 -- /___/ /\
9 -- \ \ / \
10 -- \___\/\___\
11 --
12 -- Description : This module instantiates the modules required for
13 -- reset and initialisation of the Transceiver
14 --
15 -- Module mgt11g2_tx_rx_cfpga_support
16 -- Generated by Xilinx 7 Series FPGAs Transceivers Wizard
17 --
18 --
19 -- (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
20 --
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64 
65 
66 library ieee;
67 use ieee.std_logic_1164.all;
68 use ieee.numeric_std.all;
69 use ieee.std_logic_unsigned.all;
70 library UNISIM;
71 use UNISIM.VCOMPONENTS.ALL;
72 --***********************************Entity Declaration************************
73 
74 entity mgt11g2_tx_rx_cfpga_support is
75 generic
76 (
77  EXAMPLE_SIM_GTRESET_SPEEDUP : string := "TRUE"; -- simulation setting for GT SecureIP model
78  STABLE_CLOCK_PERIOD : integer := 16
79 
80 );
81 port
82 (
83  SOFT_RESET_TX_IN : in std_logic;
84  SOFT_RESET_RX_IN : in std_logic;
85  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
86  Q1_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
87  Q1_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
88 
89  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
90  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
91  GT0_DATA_VALID_IN : in std_logic;
92  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
93  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
94  GT1_DATA_VALID_IN : in std_logic;
95  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
96  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
97  GT2_DATA_VALID_IN : in std_logic;
98  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
99  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
100  GT3_DATA_VALID_IN : in std_logic;
101 
102  GT0_TXUSRCLK_OUT : out std_logic;
103  GT0_TXUSRCLK2_OUT : out std_logic;
104  GT0_RXUSRCLK_OUT : out std_logic;
105  GT0_RXUSRCLK2_OUT : out std_logic;
106 
107  GT1_TXUSRCLK_OUT : out std_logic;
108  GT1_TXUSRCLK2_OUT : out std_logic;
109  GT1_RXUSRCLK_OUT : out std_logic;
110  GT1_RXUSRCLK2_OUT : out std_logic;
111 
112  GT2_TXUSRCLK_OUT : out std_logic;
113  GT2_TXUSRCLK2_OUT : out std_logic;
114  GT2_RXUSRCLK_OUT : out std_logic;
115  GT2_RXUSRCLK2_OUT : out std_logic;
116 
117  GT3_TXUSRCLK_OUT : out std_logic;
118  GT3_TXUSRCLK2_OUT : out std_logic;
119  GT3_RXUSRCLK_OUT : out std_logic;
120  GT3_RXUSRCLK2_OUT : out std_logic;
121 
122  --_________________________________________________________________________
123  --GT0 (X1Y4)
124  --____________________________CHANNEL PORTS________________________________
125  -------------------------- Channel - Clocking Ports ------------------------
126  gt0_gtnorthrefclk0_in : in std_logic;
127  gt0_gtnorthrefclk1_in : in std_logic;
128  gt0_gtsouthrefclk0_in : in std_logic;
129  gt0_gtsouthrefclk1_in : in std_logic;
130  ---------------------------- Channel - DRP Ports --------------------------
131  gt0_drpaddr_in : in std_logic_vector(8 downto 0);
132  gt0_drpdi_in : in std_logic_vector(15 downto 0);
133  gt0_drpdo_out : out std_logic_vector(15 downto 0);
134  gt0_drpen_in : in std_logic;
135  gt0_drprdy_out : out std_logic;
136  gt0_drpwe_in : in std_logic;
137  ------------------------------ Power-Down Ports ----------------------------
138  gt0_rxpd_in : in std_logic_vector(1 downto 0);
139  gt0_txpd_in : in std_logic_vector(1 downto 0);
140  --------------------- RX Initialization and Reset Ports --------------------
141  gt0_eyescanreset_in : in std_logic;
142  gt0_rxuserrdy_in : in std_logic;
143  -------------------------- RX Margin Analysis Ports ------------------------
144  gt0_eyescandataerror_out : out std_logic;
145  gt0_eyescantrigger_in : in std_logic;
146  ------------------- Receive Ports - Digital Monitor Ports ------------------
147  gt0_dmonitorout_out : out std_logic_vector(14 downto 0);
148  ------------------ Receive Ports - FPGA RX interface Ports -----------------
149  gt0_rxdata_out : out std_logic_vector(31 downto 0);
150  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
151  gt0_rxdisperr_out : out std_logic_vector(3 downto 0);
152  gt0_rxnotintable_out : out std_logic_vector(3 downto 0);
153  ------------------------ Receive Ports - RX AFE Ports ----------------------
154  gt0_gthrxn_in : in std_logic;
155  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
156  gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
157  gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
158  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
159  gt0_rxbyteisaligned_out : out std_logic;
160  gt0_rxbyterealign_out : out std_logic;
161  gt0_rxcommadet_out : out std_logic;
162  --------------------- Receive Ports - RX Equalizer Ports -------------------
163  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
164  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
165  --------------- Receive Ports - RX Fabric Output Control Ports -------------
166  gt0_rxoutclkfabric_out : out std_logic;
167  ------------- Receive Ports - RX Initialization and Reset Ports ------------
168  gt0_gtrxreset_in : in std_logic;
169  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
170  gt0_rxchariscomma_out : out std_logic_vector(3 downto 0);
171  gt0_rxcharisk_out : out std_logic_vector(3 downto 0);
172  ------------------------ Receive Ports -RX AFE Ports -----------------------
173  gt0_gthrxp_in : in std_logic;
174  -------------- Receive Ports -RX Initialization and Reset Ports ------------
175  gt0_rxresetdone_out : out std_logic;
176  --------------------- TX Initialization and Reset Ports --------------------
177  gt0_gttxreset_in : in std_logic;
178  gt0_txuserrdy_in : in std_logic;
179  ------------------ Transmit Ports - TX Data Path interface -----------------
180  gt0_txdata_in : in std_logic_vector(31 downto 0);
181  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
182  gt0_gthtxn_out : out std_logic;
183  gt0_gthtxp_out : out std_logic;
184  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
185  gt0_txoutclkfabric_out : out std_logic;
186  gt0_txoutclkpcs_out : out std_logic;
187  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
188  gt0_txresetdone_out : out std_logic;
189  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
190  gt0_txcharisk_in : in std_logic_vector(3 downto 0);
191 
192  --GT1 (X1Y5)
193  --____________________________CHANNEL PORTS________________________________
194  -------------------------- Channel - Clocking Ports ------------------------
195  gt1_gtnorthrefclk0_in : in std_logic;
196  gt1_gtnorthrefclk1_in : in std_logic;
197  gt1_gtsouthrefclk0_in : in std_logic;
198  gt1_gtsouthrefclk1_in : in std_logic;
199  ---------------------------- Channel - DRP Ports --------------------------
200  gt1_drpaddr_in : in std_logic_vector(8 downto 0);
201  gt1_drpdi_in : in std_logic_vector(15 downto 0);
202  gt1_drpdo_out : out std_logic_vector(15 downto 0);
203  gt1_drpen_in : in std_logic;
204  gt1_drprdy_out : out std_logic;
205  gt1_drpwe_in : in std_logic;
206  ------------------------------ Power-Down Ports ----------------------------
207  gt1_rxpd_in : in std_logic_vector(1 downto 0);
208  gt1_txpd_in : in std_logic_vector(1 downto 0);
209  --------------------- RX Initialization and Reset Ports --------------------
210  gt1_eyescanreset_in : in std_logic;
211  gt1_rxuserrdy_in : in std_logic;
212  -------------------------- RX Margin Analysis Ports ------------------------
213  gt1_eyescandataerror_out : out std_logic;
214  gt1_eyescantrigger_in : in std_logic;
215  ------------------- Receive Ports - Digital Monitor Ports ------------------
216  gt1_dmonitorout_out : out std_logic_vector(14 downto 0);
217  ------------------ Receive Ports - FPGA RX interface Ports -----------------
218  gt1_rxdata_out : out std_logic_vector(31 downto 0);
219  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
220  gt1_rxdisperr_out : out std_logic_vector(3 downto 0);
221  gt1_rxnotintable_out : out std_logic_vector(3 downto 0);
222  ------------------------ Receive Ports - RX AFE Ports ----------------------
223  gt1_gthrxn_in : in std_logic;
224  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
225  gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
226  gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
227  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
228  gt1_rxbyteisaligned_out : out std_logic;
229  gt1_rxbyterealign_out : out std_logic;
230  gt1_rxcommadet_out : out std_logic;
231  --------------------- Receive Ports - RX Equalizer Ports -------------------
232  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
233  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
234  --------------- Receive Ports - RX Fabric Output Control Ports -------------
235  gt1_rxoutclkfabric_out : out std_logic;
236  ------------- Receive Ports - RX Initialization and Reset Ports ------------
237  gt1_gtrxreset_in : in std_logic;
238  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
239  gt1_rxchariscomma_out : out std_logic_vector(3 downto 0);
240  gt1_rxcharisk_out : out std_logic_vector(3 downto 0);
241  ------------------------ Receive Ports -RX AFE Ports -----------------------
242  gt1_gthrxp_in : in std_logic;
243  -------------- Receive Ports -RX Initialization and Reset Ports ------------
244  gt1_rxresetdone_out : out std_logic;
245  --------------------- TX Initialization and Reset Ports --------------------
246  gt1_gttxreset_in : in std_logic;
247  gt1_txuserrdy_in : in std_logic;
248  ------------------ Transmit Ports - TX Data Path interface -----------------
249  gt1_txdata_in : in std_logic_vector(31 downto 0);
250  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
251  gt1_gthtxn_out : out std_logic;
252  gt1_gthtxp_out : out std_logic;
253  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
254  gt1_txoutclkfabric_out : out std_logic;
255  gt1_txoutclkpcs_out : out std_logic;
256  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
257  gt1_txresetdone_out : out std_logic;
258  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
259  gt1_txcharisk_in : in std_logic_vector(3 downto 0);
260 
261  --GT2 (X1Y6)
262  --____________________________CHANNEL PORTS________________________________
263  -------------------------- Channel - Clocking Ports ------------------------
264  gt2_gtnorthrefclk0_in : in std_logic;
265  gt2_gtnorthrefclk1_in : in std_logic;
266  gt2_gtsouthrefclk0_in : in std_logic;
267  gt2_gtsouthrefclk1_in : in std_logic;
268  ---------------------------- Channel - DRP Ports --------------------------
269  gt2_drpaddr_in : in std_logic_vector(8 downto 0);
270  gt2_drpdi_in : in std_logic_vector(15 downto 0);
271  gt2_drpdo_out : out std_logic_vector(15 downto 0);
272  gt2_drpen_in : in std_logic;
273  gt2_drprdy_out : out std_logic;
274  gt2_drpwe_in : in std_logic;
275  ------------------------------ Power-Down Ports ----------------------------
276  gt2_rxpd_in : in std_logic_vector(1 downto 0);
277  gt2_txpd_in : in std_logic_vector(1 downto 0);
278  --------------------- RX Initialization and Reset Ports --------------------
279  gt2_eyescanreset_in : in std_logic;
280  gt2_rxuserrdy_in : in std_logic;
281  -------------------------- RX Margin Analysis Ports ------------------------
282  gt2_eyescandataerror_out : out std_logic;
283  gt2_eyescantrigger_in : in std_logic;
284  ------------------- Receive Ports - Digital Monitor Ports ------------------
285  gt2_dmonitorout_out : out std_logic_vector(14 downto 0);
286  ------------------ Receive Ports - FPGA RX interface Ports -----------------
287  gt2_rxdata_out : out std_logic_vector(31 downto 0);
288  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
289  gt2_rxdisperr_out : out std_logic_vector(3 downto 0);
290  gt2_rxnotintable_out : out std_logic_vector(3 downto 0);
291  ------------------------ Receive Ports - RX AFE Ports ----------------------
292  gt2_gthrxn_in : in std_logic;
293  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
294  gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
295  gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
296  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
297  gt2_rxbyteisaligned_out : out std_logic;
298  gt2_rxbyterealign_out : out std_logic;
299  gt2_rxcommadet_out : out std_logic;
300  --------------------- Receive Ports - RX Equalizer Ports -------------------
301  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
302  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
303  --------------- Receive Ports - RX Fabric Output Control Ports -------------
304  gt2_rxoutclkfabric_out : out std_logic;
305  ------------- Receive Ports - RX Initialization and Reset Ports ------------
306  gt2_gtrxreset_in : in std_logic;
307  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
308  gt2_rxchariscomma_out : out std_logic_vector(3 downto 0);
309  gt2_rxcharisk_out : out std_logic_vector(3 downto 0);
310  ------------------------ Receive Ports -RX AFE Ports -----------------------
311  gt2_gthrxp_in : in std_logic;
312  -------------- Receive Ports -RX Initialization and Reset Ports ------------
313  gt2_rxresetdone_out : out std_logic;
314  --------------------- TX Initialization and Reset Ports --------------------
315  gt2_gttxreset_in : in std_logic;
316  gt2_txuserrdy_in : in std_logic;
317  ------------------ Transmit Ports - TX Data Path interface -----------------
318  gt2_txdata_in : in std_logic_vector(31 downto 0);
319  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
320  gt2_gthtxn_out : out std_logic;
321  gt2_gthtxp_out : out std_logic;
322  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
323  gt2_txoutclkfabric_out : out std_logic;
324  gt2_txoutclkpcs_out : out std_logic;
325  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
326  gt2_txresetdone_out : out std_logic;
327  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
328  gt2_txcharisk_in : in std_logic_vector(3 downto 0);
329 
330  --GT3 (X1Y7)
331  --____________________________CHANNEL PORTS________________________________
332  -------------------------- Channel - Clocking Ports ------------------------
333  gt3_gtnorthrefclk0_in : in std_logic;
334  gt3_gtnorthrefclk1_in : in std_logic;
335  gt3_gtsouthrefclk0_in : in std_logic;
336  gt3_gtsouthrefclk1_in : in std_logic;
337  ---------------------------- Channel - DRP Ports --------------------------
338  gt3_drpaddr_in : in std_logic_vector(8 downto 0);
339  gt3_drpdi_in : in std_logic_vector(15 downto 0);
340  gt3_drpdo_out : out std_logic_vector(15 downto 0);
341  gt3_drpen_in : in std_logic;
342  gt3_drprdy_out : out std_logic;
343  gt3_drpwe_in : in std_logic;
344  ------------------------------ Power-Down Ports ----------------------------
345  gt3_rxpd_in : in std_logic_vector(1 downto 0);
346  gt3_txpd_in : in std_logic_vector(1 downto 0);
347  --------------------- RX Initialization and Reset Ports --------------------
348  gt3_eyescanreset_in : in std_logic;
349  gt3_rxuserrdy_in : in std_logic;
350  -------------------------- RX Margin Analysis Ports ------------------------
351  gt3_eyescandataerror_out : out std_logic;
352  gt3_eyescantrigger_in : in std_logic;
353  ------------------- Receive Ports - Digital Monitor Ports ------------------
354  gt3_dmonitorout_out : out std_logic_vector(14 downto 0);
355  ------------------ Receive Ports - FPGA RX interface Ports -----------------
356  gt3_rxdata_out : out std_logic_vector(31 downto 0);
357  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
358  gt3_rxdisperr_out : out std_logic_vector(3 downto 0);
359  gt3_rxnotintable_out : out std_logic_vector(3 downto 0);
360  ------------------------ Receive Ports - RX AFE Ports ----------------------
361  gt3_gthrxn_in : in std_logic;
362  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
363  gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
364  gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
365  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
366  gt3_rxbyteisaligned_out : out std_logic;
367  gt3_rxbyterealign_out : out std_logic;
368  gt3_rxcommadet_out : out std_logic;
369  --------------------- Receive Ports - RX Equalizer Ports -------------------
370  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
371  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
372  --------------- Receive Ports - RX Fabric Output Control Ports -------------
373  gt3_rxoutclkfabric_out : out std_logic;
374  ------------- Receive Ports - RX Initialization and Reset Ports ------------
375  gt3_gtrxreset_in : in std_logic;
376  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
377  gt3_rxchariscomma_out : out std_logic_vector(3 downto 0);
378  gt3_rxcharisk_out : out std_logic_vector(3 downto 0);
379  ------------------------ Receive Ports -RX AFE Ports -----------------------
380  gt3_gthrxp_in : in std_logic;
381  -------------- Receive Ports -RX Initialization and Reset Ports ------------
382  gt3_rxresetdone_out : out std_logic;
383  --------------------- TX Initialization and Reset Ports --------------------
384  gt3_gttxreset_in : in std_logic;
385  gt3_txuserrdy_in : in std_logic;
386  ------------------ Transmit Ports - TX Data Path interface -----------------
387  gt3_txdata_in : in std_logic_vector(31 downto 0);
388  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
389  gt3_gthtxn_out : out std_logic;
390  gt3_gthtxp_out : out std_logic;
391  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
392  gt3_txoutclkfabric_out : out std_logic;
393  gt3_txoutclkpcs_out : out std_logic;
394  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
395  gt3_txresetdone_out : out std_logic;
396  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
397  gt3_txcharisk_in : in std_logic_vector(3 downto 0);
398 
399  --____________________________COMMON PORTS________________________________
400  GT0_QPLLLOCK_OUT : out std_logic;
401  GT0_QPLLREFCLKLOST_OUT : out std_logic;
402  GT0_QPLLOUTCLK_OUT : out std_logic;
403  GT0_QPLLOUTREFCLK_OUT : out std_logic;
404  sysclk_in : in std_logic
405 
406 );
407 
408 end mgt11g2_tx_rx_cfpga_support;
409 
410 architecture RTL of mgt11g2_tx_rx_cfpga_support is
411 attribute DowngradeIPIdentifiedWarnings: string;
412 attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
413 
414 --**************************Component Declarations*****************************
415 
416 component mgt11g2_tx_rx_cfpga
417 
418 port
419 (
420  SYSCLK_IN : in std_logic;
421  SOFT_RESET_TX_IN : in std_logic;
422  SOFT_RESET_RX_IN : in std_logic;
423  DONT_RESET_ON_DATA_ERROR_IN : in std_logic;
424  GT0_TX_FSM_RESET_DONE_OUT : out std_logic;
425  GT0_RX_FSM_RESET_DONE_OUT : out std_logic;
426  GT0_DATA_VALID_IN : in std_logic;
427  GT1_TX_FSM_RESET_DONE_OUT : out std_logic;
428  GT1_RX_FSM_RESET_DONE_OUT : out std_logic;
429  GT1_DATA_VALID_IN : in std_logic;
430  GT2_TX_FSM_RESET_DONE_OUT : out std_logic;
431  GT2_RX_FSM_RESET_DONE_OUT : out std_logic;
432  GT2_DATA_VALID_IN : in std_logic;
433  GT3_TX_FSM_RESET_DONE_OUT : out std_logic;
434  GT3_RX_FSM_RESET_DONE_OUT : out std_logic;
435  GT3_DATA_VALID_IN : in std_logic;
436 
437  --_________________________________________________________________________
438  --GT0 (X1Y4)
439  --____________________________CHANNEL PORTS________________________________
440  -------------------------- Channel - Clocking Ports ------------------------
441  gt0_gtnorthrefclk0_in : in std_logic;
442  gt0_gtnorthrefclk1_in : in std_logic;
443  gt0_gtsouthrefclk0_in : in std_logic;
444  gt0_gtsouthrefclk1_in : in std_logic;
445  ---------------------------- Channel - DRP Ports --------------------------
446  gt0_drpaddr_in : in std_logic_vector(8 downto 0);
447  gt0_drpclk_in : in std_logic;
448  gt0_drpdi_in : in std_logic_vector(15 downto 0);
449  gt0_drpdo_out : out std_logic_vector(15 downto 0);
450  gt0_drpen_in : in std_logic;
451  gt0_drprdy_out : out std_logic;
452  gt0_drpwe_in : in std_logic;
453  ------------------------------ Power-Down Ports ----------------------------
454  gt0_rxpd_in : in std_logic_vector(1 downto 0);
455  gt0_txpd_in : in std_logic_vector(1 downto 0);
456  --------------------- RX Initialization and Reset Ports --------------------
457  gt0_eyescanreset_in : in std_logic;
458  gt0_rxuserrdy_in : in std_logic;
459  -------------------------- RX Margin Analysis Ports ------------------------
460  gt0_eyescandataerror_out : out std_logic;
461  gt0_eyescantrigger_in : in std_logic;
462  ------------------- Receive Ports - Digital Monitor Ports ------------------
463  gt0_dmonitorout_out : out std_logic_vector(14 downto 0);
464  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
465  gt0_rxusrclk_in : in std_logic;
466  gt0_rxusrclk2_in : in std_logic;
467  ------------------ Receive Ports - FPGA RX interface Ports -----------------
468  gt0_rxdata_out : out std_logic_vector(31 downto 0);
469  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
470  gt0_rxdisperr_out : out std_logic_vector(3 downto 0);
471  gt0_rxnotintable_out : out std_logic_vector(3 downto 0);
472  ------------------------ Receive Ports - RX AFE Ports ----------------------
473  gt0_gthrxn_in : in std_logic;
474  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
475  gt0_rxphmonitor_out : out std_logic_vector(4 downto 0);
476  gt0_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
477  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
478  gt0_rxbyteisaligned_out : out std_logic;
479  gt0_rxbyterealign_out : out std_logic;
480  gt0_rxcommadet_out : out std_logic;
481  --------------------- Receive Ports - RX Equalizer Ports -------------------
482  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
483  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
484  --------------- Receive Ports - RX Fabric Output Control Ports -------------
485  gt0_rxoutclk_out : out std_logic;
486  gt0_rxoutclkfabric_out : out std_logic;
487  ------------- Receive Ports - RX Initialization and Reset Ports ------------
488  gt0_gtrxreset_in : in std_logic;
489  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
490  gt0_rxchariscomma_out : out std_logic_vector(3 downto 0);
491  gt0_rxcharisk_out : out std_logic_vector(3 downto 0);
492  ------------------------ Receive Ports -RX AFE Ports -----------------------
493  gt0_gthrxp_in : in std_logic;
494  -------------- Receive Ports -RX Initialization and Reset Ports ------------
495  gt0_rxresetdone_out : out std_logic;
496  --------------------- TX Initialization and Reset Ports --------------------
497  gt0_gttxreset_in : in std_logic;
498  gt0_txuserrdy_in : in std_logic;
499  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
500  gt0_txusrclk_in : in std_logic;
501  gt0_txusrclk2_in : in std_logic;
502  ------------------ Transmit Ports - TX Data Path interface -----------------
503  gt0_txdata_in : in std_logic_vector(31 downto 0);
504  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
505  gt0_gthtxn_out : out std_logic;
506  gt0_gthtxp_out : out std_logic;
507  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
508  gt0_txoutclk_out : out std_logic;
509  gt0_txoutclkfabric_out : out std_logic;
510  gt0_txoutclkpcs_out : out std_logic;
511  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
512  gt0_txresetdone_out : out std_logic;
513  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
514  gt0_txcharisk_in : in std_logic_vector(3 downto 0);
515 
516  --GT1 (X1Y5)
517  --____________________________CHANNEL PORTS________________________________
518  -------------------------- Channel - Clocking Ports ------------------------
519  gt1_gtnorthrefclk0_in : in std_logic;
520  gt1_gtnorthrefclk1_in : in std_logic;
521  gt1_gtsouthrefclk0_in : in std_logic;
522  gt1_gtsouthrefclk1_in : in std_logic;
523  ---------------------------- Channel - DRP Ports --------------------------
524  gt1_drpaddr_in : in std_logic_vector(8 downto 0);
525  gt1_drpclk_in : in std_logic;
526  gt1_drpdi_in : in std_logic_vector(15 downto 0);
527  gt1_drpdo_out : out std_logic_vector(15 downto 0);
528  gt1_drpen_in : in std_logic;
529  gt1_drprdy_out : out std_logic;
530  gt1_drpwe_in : in std_logic;
531  ------------------------------ Power-Down Ports ----------------------------
532  gt1_rxpd_in : in std_logic_vector(1 downto 0);
533  gt1_txpd_in : in std_logic_vector(1 downto 0);
534  --------------------- RX Initialization and Reset Ports --------------------
535  gt1_eyescanreset_in : in std_logic;
536  gt1_rxuserrdy_in : in std_logic;
537  -------------------------- RX Margin Analysis Ports ------------------------
538  gt1_eyescandataerror_out : out std_logic;
539  gt1_eyescantrigger_in : in std_logic;
540  ------------------- Receive Ports - Digital Monitor Ports ------------------
541  gt1_dmonitorout_out : out std_logic_vector(14 downto 0);
542  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
543  gt1_rxusrclk_in : in std_logic;
544  gt1_rxusrclk2_in : in std_logic;
545  ------------------ Receive Ports - FPGA RX interface Ports -----------------
546  gt1_rxdata_out : out std_logic_vector(31 downto 0);
547  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
548  gt1_rxdisperr_out : out std_logic_vector(3 downto 0);
549  gt1_rxnotintable_out : out std_logic_vector(3 downto 0);
550  ------------------------ Receive Ports - RX AFE Ports ----------------------
551  gt1_gthrxn_in : in std_logic;
552  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
553  gt1_rxphmonitor_out : out std_logic_vector(4 downto 0);
554  gt1_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
555  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
556  gt1_rxbyteisaligned_out : out std_logic;
557  gt1_rxbyterealign_out : out std_logic;
558  gt1_rxcommadet_out : out std_logic;
559  --------------------- Receive Ports - RX Equalizer Ports -------------------
560  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
561  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
562  --------------- Receive Ports - RX Fabric Output Control Ports -------------
563  gt1_rxoutclk_out : out std_logic;
564  gt1_rxoutclkfabric_out : out std_logic;
565  ------------- Receive Ports - RX Initialization and Reset Ports ------------
566  gt1_gtrxreset_in : in std_logic;
567  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
568  gt1_rxchariscomma_out : out std_logic_vector(3 downto 0);
569  gt1_rxcharisk_out : out std_logic_vector(3 downto 0);
570  ------------------------ Receive Ports -RX AFE Ports -----------------------
571  gt1_gthrxp_in : in std_logic;
572  -------------- Receive Ports -RX Initialization and Reset Ports ------------
573  gt1_rxresetdone_out : out std_logic;
574  --------------------- TX Initialization and Reset Ports --------------------
575  gt1_gttxreset_in : in std_logic;
576  gt1_txuserrdy_in : in std_logic;
577  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
578  gt1_txusrclk_in : in std_logic;
579  gt1_txusrclk2_in : in std_logic;
580  ------------------ Transmit Ports - TX Data Path interface -----------------
581  gt1_txdata_in : in std_logic_vector(31 downto 0);
582  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
583  gt1_gthtxn_out : out std_logic;
584  gt1_gthtxp_out : out std_logic;
585  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
586  gt1_txoutclk_out : out std_logic;
587  gt1_txoutclkfabric_out : out std_logic;
588  gt1_txoutclkpcs_out : out std_logic;
589  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
590  gt1_txresetdone_out : out std_logic;
591  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
592  gt1_txcharisk_in : in std_logic_vector(3 downto 0);
593 
594  --GT2 (X1Y6)
595  --____________________________CHANNEL PORTS________________________________
596  -------------------------- Channel - Clocking Ports ------------------------
597  gt2_gtnorthrefclk0_in : in std_logic;
598  gt2_gtnorthrefclk1_in : in std_logic;
599  gt2_gtsouthrefclk0_in : in std_logic;
600  gt2_gtsouthrefclk1_in : in std_logic;
601  ---------------------------- Channel - DRP Ports --------------------------
602  gt2_drpaddr_in : in std_logic_vector(8 downto 0);
603  gt2_drpclk_in : in std_logic;
604  gt2_drpdi_in : in std_logic_vector(15 downto 0);
605  gt2_drpdo_out : out std_logic_vector(15 downto 0);
606  gt2_drpen_in : in std_logic;
607  gt2_drprdy_out : out std_logic;
608  gt2_drpwe_in : in std_logic;
609 
610  ------------------------------ Power-Down Ports ----------------------------
611  gt2_rxpd_in : in std_logic_vector(1 downto 0);
612  gt2_txpd_in : in std_logic_vector(1 downto 0);
613  --------------------- RX Initialization and Reset Ports --------------------
614  gt2_eyescanreset_in : in std_logic;
615  gt2_rxuserrdy_in : in std_logic;
616  -------------------------- RX Margin Analysis Ports ------------------------
617  gt2_eyescandataerror_out : out std_logic;
618  gt2_eyescantrigger_in : in std_logic;
619  ------------------- Receive Ports - Digital Monitor Ports ------------------
620  gt2_dmonitorout_out : out std_logic_vector(14 downto 0);
621  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
622  gt2_rxusrclk_in : in std_logic;
623  gt2_rxusrclk2_in : in std_logic;
624  ------------------ Receive Ports - FPGA RX interface Ports -----------------
625  gt2_rxdata_out : out std_logic_vector(31 downto 0);
626  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
627  gt2_rxdisperr_out : out std_logic_vector(3 downto 0);
628  gt2_rxnotintable_out : out std_logic_vector(3 downto 0);
629  ------------------------ Receive Ports - RX AFE Ports ----------------------
630  gt2_gthrxn_in : in std_logic;
631  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
632  gt2_rxphmonitor_out : out std_logic_vector(4 downto 0);
633  gt2_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
634  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
635  gt2_rxbyteisaligned_out : out std_logic;
636  gt2_rxbyterealign_out : out std_logic;
637  gt2_rxcommadet_out : out std_logic;
638  --------------------- Receive Ports - RX Equalizer Ports -------------------
639  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
640  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
641  --------------- Receive Ports - RX Fabric Output Control Ports -------------
642  gt2_rxoutclk_out : out std_logic;
643  gt2_rxoutclkfabric_out : out std_logic;
644  ------------- Receive Ports - RX Initialization and Reset Ports ------------
645  gt2_gtrxreset_in : in std_logic;
646  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
647  gt2_rxchariscomma_out : out std_logic_vector(3 downto 0);
648  gt2_rxcharisk_out : out std_logic_vector(3 downto 0);
649  ------------------------ Receive Ports -RX AFE Ports -----------------------
650  gt2_gthrxp_in : in std_logic;
651  -------------- Receive Ports -RX Initialization and Reset Ports ------------
652  gt2_rxresetdone_out : out std_logic;
653  --------------------- TX Initialization and Reset Ports --------------------
654  gt2_gttxreset_in : in std_logic;
655  gt2_txuserrdy_in : in std_logic;
656  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
657  gt2_txusrclk_in : in std_logic;
658  gt2_txusrclk2_in : in std_logic;
659  ------------------ Transmit Ports - TX Data Path interface -----------------
660  gt2_txdata_in : in std_logic_vector(31 downto 0);
661  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
662  gt2_gthtxn_out : out std_logic;
663  gt2_gthtxp_out : out std_logic;
664  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
665  gt2_txoutclk_out : out std_logic;
666  gt2_txoutclkfabric_out : out std_logic;
667  gt2_txoutclkpcs_out : out std_logic;
668  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
669  gt2_txresetdone_out : out std_logic;
670  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
671  gt2_txcharisk_in : in std_logic_vector(3 downto 0);
672 
673  --GT3 (X1Y7)
674  --____________________________CHANNEL PORTS________________________________
675  -------------------------- Channel - Clocking Ports ------------------------
676  gt3_gtnorthrefclk0_in : in std_logic;
677  gt3_gtnorthrefclk1_in : in std_logic;
678  gt3_gtsouthrefclk0_in : in std_logic;
679  gt3_gtsouthrefclk1_in : in std_logic;
680  ---------------------------- Channel - DRP Ports --------------------------
681  gt3_drpclk_in : in std_logic;
682  ------------------------------ Power-Down Ports ----------------------------
683  gt3_rxpd_in : in std_logic_vector(1 downto 0);
684  gt3_txpd_in : in std_logic_vector(1 downto 0);
685  --------------------- RX Initialization and Reset Ports --------------------
686  gt3_eyescanreset_in : in std_logic;
687  gt3_rxuserrdy_in : in std_logic;
688  -------------------------- RX Margin Analysis Ports ------------------------
689  gt3_eyescandataerror_out : out std_logic;
690  gt3_eyescantrigger_in : in std_logic;
691  ------------------- Receive Ports - Digital Monitor Ports ------------------
692  gt3_dmonitorout_out : out std_logic_vector(14 downto 0);
693  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
694  gt3_rxusrclk_in : in std_logic;
695  gt3_rxusrclk2_in : in std_logic;
696  ------------------ Receive Ports - FPGA RX interface Ports -----------------
697  gt3_rxdata_out : out std_logic_vector(31 downto 0);
698  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
699  gt3_rxdisperr_out : out std_logic_vector(3 downto 0);
700  gt3_rxnotintable_out : out std_logic_vector(3 downto 0);
701  ------------------------ Receive Ports - RX AFE Ports ----------------------
702  gt3_gthrxn_in : in std_logic;
703  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
704  gt3_rxphmonitor_out : out std_logic_vector(4 downto 0);
705  gt3_rxphslipmonitor_out : out std_logic_vector(4 downto 0);
706  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
707  gt3_rxbyteisaligned_out : out std_logic;
708  gt3_rxbyterealign_out : out std_logic;
709  gt3_rxcommadet_out : out std_logic;
710  --------------------- Receive Ports - RX Equalizer Ports -------------------
711  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
712  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
713  --------------- Receive Ports - RX Fabric Output Control Ports -------------
714  gt3_rxoutclk_out : out std_logic;
715  gt3_rxoutclkfabric_out : out std_logic;
716  ------------- Receive Ports - RX Initialization and Reset Ports ------------
717  gt3_gtrxreset_in : in std_logic;
718  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
719  gt3_rxchariscomma_out : out std_logic_vector(3 downto 0);
720  gt3_rxcharisk_out : out std_logic_vector(3 downto 0);
721  ------------------------ Receive Ports -RX AFE Ports -----------------------
722  gt3_gthrxp_in : in std_logic;
723  ------------------------ Receive Ports -RX AFE Ports -----------------------
724  gt3_drpaddr_in : in std_logic_vector(8 downto 0);
725  gt3_drpdi_in : in std_logic_vector(15 downto 0);
726  gt3_drpdo_out : out std_logic_vector(15 downto 0);
727  gt3_drpen_in : in std_logic;
728  gt3_drprdy_out : out std_logic;
729  gt3_drpwe_in : in std_logic;
730 
731  -------------- Receive Ports -RX Initialization and Reset Ports ------------
732  gt3_rxresetdone_out : out std_logic;
733  --------------------- TX Initialization and Reset Ports --------------------
734  gt3_gttxreset_in : in std_logic;
735  gt3_txuserrdy_in : in std_logic;
736  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
737  gt3_txusrclk_in : in std_logic;
738  gt3_txusrclk2_in : in std_logic;
739  ------------------ Transmit Ports - TX Data Path interface -----------------
740  gt3_txdata_in : in std_logic_vector(31 downto 0);
741  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
742  gt3_gthtxn_out : out std_logic;
743  gt3_gthtxp_out : out std_logic;
744  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
745  gt3_txoutclk_out : out std_logic;
746  gt3_txoutclkfabric_out : out std_logic;
747  gt3_txoutclkpcs_out : out std_logic;
748  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
749  gt3_txresetdone_out : out std_logic;
750  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
751  gt3_txcharisk_in : in std_logic_vector(3 downto 0);
752 
753 
754  --____________________________COMMON PORTS________________________________
755  GT0_QPLLLOCK_IN : in std_logic;
756  GT0_QPLLREFCLKLOST_IN : in std_logic;
757  GT0_QPLLRESET_OUT : out std_logic;
758  GT0_QPLLOUTCLK_IN : in std_logic;
759  GT0_QPLLOUTREFCLK_IN : in std_logic
760 
761 );
762 
763 end component;
764 
765 component mgt11g2_tx_rx_cfpga_common_reset
766 generic
767 (
768  STABLE_CLOCK_PERIOD : integer := 8 -- Period of the stable clock driving this state-machine, unit is [ns]
769  );
770 port
771  (
772  STABLE_CLOCK : in std_logic; --Stable Clock, either a stable clock from the PCB
773  SOFT_RESET : in std_logic; --User Reset, can be pulled any time
774  COMMON_RESET : out std_logic --Reset QPLL
775  );
776 end component;
777 
778 component mgt11g2_tx_rx_cfpga_common
779 generic
780 (
781  -- Simulation attributes
782  WRAPPER_SIM_GTRESET_SPEEDUP : string := "FALSE" ; -- Set to "TRUE" to speed up sim reset
783  SIM_QPLLREFCLK_SEL :bit_vector := "001"
784 
785 );
786 port
787 (
788  GTGREFCLK_IN : in std_logic;
789  GTNORTHREFCLK0_IN : in std_logic;
790  GTNORTHREFCLK1_IN : in std_logic;
791  GTSOUTHREFCLK0_IN : in std_logic;
792  GTSOUTHREFCLK1_IN : in std_logic;
793  QPLLREFCLKSEL_IN : in std_logic_vector(2 downto 0);
794  GTREFCLK0_IN : in std_logic;
795  GTREFCLK1_IN : in std_logic;
796  QPLLLOCK_OUT : out std_logic;
797  QPLLLOCKDETCLK_IN : in std_logic;
798  QPLLOUTCLK_OUT : out std_logic;
799  QPLLOUTREFCLK_OUT : out std_logic;
800  QPLLREFCLKLOST_OUT : out std_logic;
801  QPLLRESET_IN : in std_logic
802 
803 );
804 
805 end component;
806 
807 component mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE
808 port
809 (
810 
811  GT0_TXUSRCLK_OUT : out std_logic;
812  GT0_TXUSRCLK2_OUT : out std_logic;
813  GT0_TXOUTCLK_IN : in std_logic;
814  GT0_RXUSRCLK_OUT : out std_logic;
815  GT0_RXUSRCLK2_OUT : out std_logic;
816  GT0_RXOUTCLK_IN : in std_logic;
817 
818  GT1_TXUSRCLK_OUT : out std_logic;
819  GT1_TXUSRCLK2_OUT : out std_logic;
820  GT1_TXOUTCLK_IN : in std_logic;
821  GT1_RXUSRCLK_OUT : out std_logic;
822  GT1_RXUSRCLK2_OUT : out std_logic;
823  GT1_RXOUTCLK_IN : in std_logic;
824 
825  GT2_TXUSRCLK_OUT : out std_logic;
826  GT2_TXUSRCLK2_OUT : out std_logic;
827  GT2_TXOUTCLK_IN : in std_logic;
828  GT2_RXUSRCLK_OUT : out std_logic;
829  GT2_RXUSRCLK2_OUT : out std_logic;
830  GT2_RXOUTCLK_IN : in std_logic;
831 
832  GT3_TXUSRCLK_OUT : out std_logic;
833  GT3_TXUSRCLK2_OUT : out std_logic;
834  GT3_TXOUTCLK_IN : in std_logic;
835  GT3_RXUSRCLK_OUT : out std_logic;
836  GT3_RXUSRCLK2_OUT : out std_logic;
837  GT3_RXOUTCLK_IN : in std_logic;
838  Q1_CLK1_GTREFCLK_PAD_N_IN : in std_logic;
839  Q1_CLK1_GTREFCLK_PAD_P_IN : in std_logic;
840  Q1_CLK1_GTREFCLK_OUT : out std_logic
841 );
842 end component;
843 
844 --***********************************Parameter Declarations********************
845 
846  constant DLY : time := 1 ns;
847 
848 --************************** Register Declarations ****************************
849 
850  signal gt0_txfsmresetdone_i : std_logic;
851 signal gt0_rxfsmresetdone_i : std_logic;
852  signal gt0_txfsmresetdone_r : std_logic;
853  signal gt0_txfsmresetdone_r2 : std_logic;
854 signal gt0_rxresetdone_r : std_logic;
855 signal gt0_rxresetdone_r2 : std_logic;
856 signal gt0_rxresetdone_r3 : std_logic;
857 
858 
859  signal gt1_txfsmresetdone_i : std_logic;
860 signal gt1_rxfsmresetdone_i : std_logic;
861  signal gt1_txfsmresetdone_r : std_logic;
862  signal gt1_txfsmresetdone_r2 : std_logic;
863 signal gt1_rxresetdone_r : std_logic;
864 signal gt1_rxresetdone_r2 : std_logic;
865 signal gt1_rxresetdone_r3 : std_logic;
866 
867 
868  signal gt2_txfsmresetdone_i : std_logic;
869 signal gt2_rxfsmresetdone_i : std_logic;
870  signal gt2_txfsmresetdone_r : std_logic;
871  signal gt2_txfsmresetdone_r2 : std_logic;
872 signal gt2_rxresetdone_r : std_logic;
873 signal gt2_rxresetdone_r2 : std_logic;
874 signal gt2_rxresetdone_r3 : std_logic;
875 
876 
877  signal gt3_txfsmresetdone_i : std_logic;
878 signal gt3_rxfsmresetdone_i : std_logic;
879  signal gt3_txfsmresetdone_r : std_logic;
880  signal gt3_txfsmresetdone_r2 : std_logic;
881 signal gt3_rxresetdone_r : std_logic;
882 signal gt3_rxresetdone_r2 : std_logic;
883 signal gt3_rxresetdone_r3 : std_logic;
884 
885 
886 signal reset_pulse : std_logic_vector(3 downto 0);
887  signal reset_counter : unsigned(5 downto 0) := "000000";
888 
889 --**************************** Wire Declarations ******************************
890  -------------------------- GT Wrapper Wires ------------------------------
891  --________________________________________________________________________
892  --________________________________________________________________________
893  --GT0 (X1Y4)
894 
895  -------------------------- Channel - Clocking Ports ------------------------
896  signal gt0_gtnorthrefclk0_i : std_logic;
897  signal gt0_gtnorthrefclk1_i : std_logic;
898  signal gt0_gtsouthrefclk0_i : std_logic;
899  signal gt0_gtsouthrefclk1_i : std_logic;
900  ------------------------------ Power-Down Ports ----------------------------
901  signal gt0_rxpd_i : std_logic_vector(1 downto 0);
902  signal gt0_txpd_i : std_logic_vector(1 downto 0);
903  --------------------- RX Initialization and Reset Ports --------------------
904  signal gt0_eyescanreset_i : std_logic;
905  signal gt0_rxuserrdy_i : std_logic;
906  -------------------------- RX Margin Analysis Ports ------------------------
907  signal gt0_eyescandataerror_i : std_logic;
908  signal gt0_eyescantrigger_i : std_logic;
909  ------------------- Receive Ports - Digital Monitor Ports ------------------
910  signal gt0_dmonitorout_i : std_logic_vector(14 downto 0);
911  ------------------ Receive Ports - FPGA RX interface Ports -----------------
912  signal gt0_rxdata_i : std_logic_vector(31 downto 0);
913  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
914  signal gt0_rxdisperr_i : std_logic_vector(3 downto 0);
915  signal gt0_rxnotintable_i : std_logic_vector(3 downto 0);
916  ------------------------ Receive Ports - RX AFE Ports ----------------------
917  signal gt0_gthrxn_i : std_logic;
918  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
919  signal gt0_rxdlyen_i : std_logic;
920  signal gt0_rxdlysreset_i : std_logic;
921  signal gt0_rxdlysresetdone_i : std_logic;
922  signal gt0_rxphalign_i : std_logic;
923  signal gt0_rxphaligndone_i : std_logic;
924  signal gt0_rxphalignen_i : std_logic;
925  signal gt0_rxphdlyreset_i : std_logic;
926  signal gt0_rxphmonitor_i : std_logic_vector(4 downto 0);
927  signal gt0_rxphslipmonitor_i : std_logic_vector(4 downto 0);
928  signal gt0_rxsyncallin_i : std_logic;
929  signal gt0_rxsyncdone_i : std_logic;
930  signal gt0_rxsyncin_i : std_logic;
931  signal gt0_rxsyncmode_i : std_logic;
932  signal gt0_rxsyncout_i : std_logic;
933  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
934  signal gt0_rxbyteisaligned_i : std_logic;
935  signal gt0_rxbyterealign_i : std_logic;
936  signal gt0_rxcommadet_i : std_logic;
937  --------------------- Receive Ports - RX Equalizer Ports -------------------
938  signal gt0_rxdfeagchold_i : std_logic;
939  signal gt0_rxdfelfhold_i : std_logic;
940  signal gt0_rxmonitorout_i : std_logic_vector(6 downto 0);
941  signal gt0_rxmonitorsel_i : std_logic_vector(1 downto 0);
942  --------------- Receive Ports - RX Fabric Output Control Ports -------------
943  signal gt0_rxoutclk_i : std_logic;
944  signal gt0_rxoutclkfabric_i : std_logic;
945  ------------- Receive Ports - RX Initialization and Reset Ports ------------
946  signal gt0_gtrxreset_i : std_logic;
947  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
948  signal gt0_rxchariscomma_i : std_logic_vector(3 downto 0);
949  signal gt0_rxcharisk_i : std_logic_vector(3 downto 0);
950  ------------------------ Receive Ports -RX AFE Ports -----------------------
951  signal gt0_gthrxp_i : std_logic;
952  -------------- Receive Ports -RX Initialization and Reset Ports ------------
953  signal gt0_rxresetdone_i : std_logic;
954  --------------------- TX Initialization and Reset Ports --------------------
955  signal gt0_gttxreset_i : std_logic;
956  signal gt0_txuserrdy_i : std_logic;
957  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
958  signal gt0_txdlyen_i : std_logic;
959  signal gt0_txdlysreset_i : std_logic;
960  signal gt0_txdlysresetdone_i : std_logic;
961  signal gt0_txphalign_i : std_logic;
962  signal gt0_txphaligndone_i : std_logic;
963  signal gt0_txphalignen_i : std_logic;
964  signal gt0_txphdlyreset_i : std_logic;
965  signal gt0_txphinit_i : std_logic;
966  signal gt0_txphinitdone_i : std_logic;
967  ------------------ Transmit Ports - TX Data Path interface -----------------
968  signal gt0_txdata_i : std_logic_vector(31 downto 0);
969  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
970  signal gt0_gthtxn_i : std_logic;
971  signal gt0_gthtxp_i : std_logic;
972  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
973  signal gt0_txoutclk_i : std_logic;
974  signal gt0_txoutclkfabric_i : std_logic;
975  signal gt0_txoutclkpcs_i : std_logic;
976  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
977  signal gt0_txresetdone_i : std_logic;
978  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
979  signal gt0_txcharisk_i : std_logic_vector(3 downto 0);
980 
981  --________________________________________________________________________
982  --________________________________________________________________________
983  --GT1 (X1Y5)
984 
985  -------------------------- Channel - Clocking Ports ------------------------
986  signal gt1_gtnorthrefclk0_i : std_logic;
987  signal gt1_gtnorthrefclk1_i : std_logic;
988  signal gt1_gtsouthrefclk0_i : std_logic;
989  signal gt1_gtsouthrefclk1_i : std_logic;
990  ------------------------------ Power-Down Ports ----------------------------
991  signal gt1_rxpd_i : std_logic_vector(1 downto 0);
992  signal gt1_txpd_i : std_logic_vector(1 downto 0);
993  --------------------- RX Initialization and Reset Ports --------------------
994  signal gt1_eyescanreset_i : std_logic;
995  signal gt1_rxuserrdy_i : std_logic;
996  -------------------------- RX Margin Analysis Ports ------------------------
997  signal gt1_eyescandataerror_i : std_logic;
998  signal gt1_eyescantrigger_i : std_logic;
999  ------------------- Receive Ports - Digital Monitor Ports ------------------
1000  signal gt1_dmonitorout_i : std_logic_vector(14 downto 0);
1001  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1002  signal gt1_rxdata_i : std_logic_vector(31 downto 0);
1003  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1004  signal gt1_rxdisperr_i : std_logic_vector(3 downto 0);
1005  signal gt1_rxnotintable_i : std_logic_vector(3 downto 0);
1006  ------------------------ Receive Ports - RX AFE Ports ----------------------
1007  signal gt1_gthrxn_i : std_logic;
1008  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1009  signal gt1_rxdlyen_i : std_logic;
1010  signal gt1_rxdlysreset_i : std_logic;
1011  signal gt1_rxdlysresetdone_i : std_logic;
1012  signal gt1_rxphalign_i : std_logic;
1013  signal gt1_rxphaligndone_i : std_logic;
1014  signal gt1_rxphalignen_i : std_logic;
1015  signal gt1_rxphdlyreset_i : std_logic;
1016  signal gt1_rxphmonitor_i : std_logic_vector(4 downto 0);
1017  signal gt1_rxphslipmonitor_i : std_logic_vector(4 downto 0);
1018  signal gt1_rxsyncallin_i : std_logic;
1019  signal gt1_rxsyncdone_i : std_logic;
1020  signal gt1_rxsyncin_i : std_logic;
1021  signal gt1_rxsyncmode_i : std_logic;
1022  signal gt1_rxsyncout_i : std_logic;
1023  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1024  signal gt1_rxbyteisaligned_i : std_logic;
1025  signal gt1_rxbyterealign_i : std_logic;
1026  signal gt1_rxcommadet_i : std_logic;
1027  --------------------- Receive Ports - RX Equalizer Ports -------------------
1028  signal gt1_rxdfeagchold_i : std_logic;
1029  signal gt1_rxdfelfhold_i : std_logic;
1030  signal gt1_rxmonitorout_i : std_logic_vector(6 downto 0);
1031  signal gt1_rxmonitorsel_i : std_logic_vector(1 downto 0);
1032  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1033  signal gt1_rxoutclk_i : std_logic;
1034  signal gt1_rxoutclkfabric_i : std_logic;
1035  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1036  signal gt1_gtrxreset_i : std_logic;
1037  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1038  signal gt1_rxchariscomma_i : std_logic_vector(3 downto 0);
1039  signal gt1_rxcharisk_i : std_logic_vector(3 downto 0);
1040  ------------------------ Receive Ports -RX AFE Ports -----------------------
1041  signal gt1_gthrxp_i : std_logic;
1042  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1043  signal gt1_rxresetdone_i : std_logic;
1044  --------------------- TX Initialization and Reset Ports --------------------
1045  signal gt1_gttxreset_i : std_logic;
1046  signal gt1_txuserrdy_i : std_logic;
1047  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
1048  signal gt1_txdlyen_i : std_logic;
1049  signal gt1_txdlysreset_i : std_logic;
1050  signal gt1_txdlysresetdone_i : std_logic;
1051  signal gt1_txphalign_i : std_logic;
1052  signal gt1_txphaligndone_i : std_logic;
1053  signal gt1_txphalignen_i : std_logic;
1054  signal gt1_txphdlyreset_i : std_logic;
1055  signal gt1_txphinit_i : std_logic;
1056  signal gt1_txphinitdone_i : std_logic;
1057  ------------------ Transmit Ports - TX Data Path interface -----------------
1058  signal gt1_txdata_i : std_logic_vector(31 downto 0);
1059  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1060  signal gt1_gthtxn_i : std_logic;
1061  signal gt1_gthtxp_i : std_logic;
1062  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1063  signal gt1_txoutclk_i : std_logic;
1064  signal gt1_txoutclkfabric_i : std_logic;
1065  signal gt1_txoutclkpcs_i : std_logic;
1066  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1067  signal gt1_txresetdone_i : std_logic;
1068  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1069  signal gt1_txcharisk_i : std_logic_vector(3 downto 0);
1070 
1071  --________________________________________________________________________
1072  --________________________________________________________________________
1073  --GT2 (X1Y6)
1074 
1075  -------------------------- Channel - Clocking Ports ------------------------
1076  signal gt2_gtnorthrefclk0_i : std_logic;
1077  signal gt2_gtnorthrefclk1_i : std_logic;
1078  signal gt2_gtsouthrefclk0_i : std_logic;
1079  signal gt2_gtsouthrefclk1_i : std_logic;
1080  ------------------------------ Power-Down Ports ----------------------------
1081  signal gt2_rxpd_i : std_logic_vector(1 downto 0);
1082  signal gt2_txpd_i : std_logic_vector(1 downto 0);
1083  --------------------- RX Initialization and Reset Ports --------------------
1084  signal gt2_eyescanreset_i : std_logic;
1085  signal gt2_rxuserrdy_i : std_logic;
1086  -------------------------- RX Margin Analysis Ports ------------------------
1087  signal gt2_eyescandataerror_i : std_logic;
1088  signal gt2_eyescantrigger_i : std_logic;
1089  ------------------- Receive Ports - Digital Monitor Ports ------------------
1090  signal gt2_dmonitorout_i : std_logic_vector(14 downto 0);
1091  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1092  signal gt2_rxdata_i : std_logic_vector(31 downto 0);
1093  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1094  signal gt2_rxdisperr_i : std_logic_vector(3 downto 0);
1095  signal gt2_rxnotintable_i : std_logic_vector(3 downto 0);
1096  ------------------------ Receive Ports - RX AFE Ports ----------------------
1097  signal gt2_gthrxn_i : std_logic;
1098  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1099  signal gt2_rxdlyen_i : std_logic;
1100  signal gt2_rxdlysreset_i : std_logic;
1101  signal gt2_rxdlysresetdone_i : std_logic;
1102  signal gt2_rxphalign_i : std_logic;
1103  signal gt2_rxphaligndone_i : std_logic;
1104  signal gt2_rxphalignen_i : std_logic;
1105  signal gt2_rxphdlyreset_i : std_logic;
1106  signal gt2_rxphmonitor_i : std_logic_vector(4 downto 0);
1107  signal gt2_rxphslipmonitor_i : std_logic_vector(4 downto 0);
1108  signal gt2_rxsyncallin_i : std_logic;
1109  signal gt2_rxsyncdone_i : std_logic;
1110  signal gt2_rxsyncin_i : std_logic;
1111  signal gt2_rxsyncmode_i : std_logic;
1112  signal gt2_rxsyncout_i : std_logic;
1113  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1114  signal gt2_rxbyteisaligned_i : std_logic;
1115  signal gt2_rxbyterealign_i : std_logic;
1116  signal gt2_rxcommadet_i : std_logic;
1117  --------------------- Receive Ports - RX Equalizer Ports -------------------
1118  signal gt2_rxdfeagchold_i : std_logic;
1119  signal gt2_rxdfelfhold_i : std_logic;
1120  signal gt2_rxmonitorout_i : std_logic_vector(6 downto 0);
1121  signal gt2_rxmonitorsel_i : std_logic_vector(1 downto 0);
1122  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1123  signal gt2_rxoutclk_i : std_logic;
1124  signal gt2_rxoutclkfabric_i : std_logic;
1125  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1126  signal gt2_gtrxreset_i : std_logic;
1127  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1128  signal gt2_rxchariscomma_i : std_logic_vector(3 downto 0);
1129  signal gt2_rxcharisk_i : std_logic_vector(3 downto 0);
1130  ------------------------ Receive Ports -RX AFE Ports -----------------------
1131  signal gt2_gthrxp_i : std_logic;
1132  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1133  signal gt2_rxresetdone_i : std_logic;
1134  --------------------- TX Initialization and Reset Ports --------------------
1135  signal gt2_gttxreset_i : std_logic;
1136  signal gt2_txuserrdy_i : std_logic;
1137  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
1138  signal gt2_txdlyen_i : std_logic;
1139  signal gt2_txdlysreset_i : std_logic;
1140  signal gt2_txdlysresetdone_i : std_logic;
1141  signal gt2_txphalign_i : std_logic;
1142  signal gt2_txphaligndone_i : std_logic;
1143  signal gt2_txphalignen_i : std_logic;
1144  signal gt2_txphdlyreset_i : std_logic;
1145  signal gt2_txphinit_i : std_logic;
1146  signal gt2_txphinitdone_i : std_logic;
1147  ------------------ Transmit Ports - TX Data Path interface -----------------
1148  signal gt2_txdata_i : std_logic_vector(31 downto 0);
1149  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1150  signal gt2_gthtxn_i : std_logic;
1151  signal gt2_gthtxp_i : std_logic;
1152  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1153  signal gt2_txoutclk_i : std_logic;
1154  signal gt2_txoutclkfabric_i : std_logic;
1155  signal gt2_txoutclkpcs_i : std_logic;
1156  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1157  signal gt2_txresetdone_i : std_logic;
1158  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1159  signal gt2_txcharisk_i : std_logic_vector(3 downto 0);
1160 
1161  --________________________________________________________________________
1162  --________________________________________________________________________
1163  --GT3 (X1Y7)
1164 
1165  -------------------------- Channel - Clocking Ports ------------------------
1166  signal gt3_gtnorthrefclk0_i : std_logic;
1167  signal gt3_gtnorthrefclk1_i : std_logic;
1168  signal gt3_gtsouthrefclk0_i : std_logic;
1169  signal gt3_gtsouthrefclk1_i : std_logic;
1170  ------------------------------ Power-Down Ports ----------------------------
1171  signal gt3_rxpd_i : std_logic_vector(1 downto 0);
1172  signal gt3_txpd_i : std_logic_vector(1 downto 0);
1173  --------------------- RX Initialization and Reset Ports --------------------
1174  signal gt3_eyescanreset_i : std_logic;
1175  signal gt3_rxuserrdy_i : std_logic;
1176  -------------------------- RX Margin Analysis Ports ------------------------
1177  signal gt3_eyescandataerror_i : std_logic;
1178  signal gt3_eyescantrigger_i : std_logic;
1179  ------------------- Receive Ports - Digital Monitor Ports ------------------
1180  signal gt3_dmonitorout_i : std_logic_vector(14 downto 0);
1181  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1182  signal gt3_rxdata_i : std_logic_vector(31 downto 0);
1183  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1184  signal gt3_rxdisperr_i : std_logic_vector(3 downto 0);
1185  signal gt3_rxnotintable_i : std_logic_vector(3 downto 0);
1186  ------------------------ Receive Ports - RX AFE Ports ----------------------
1187  signal gt3_gthrxn_i : std_logic;
1188  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1189  signal gt3_rxdlyen_i : std_logic;
1190  signal gt3_rxdlysreset_i : std_logic;
1191  signal gt3_rxdlysresetdone_i : std_logic;
1192  signal gt3_rxphalign_i : std_logic;
1193  signal gt3_rxphaligndone_i : std_logic;
1194  signal gt3_rxphalignen_i : std_logic;
1195  signal gt3_rxphdlyreset_i : std_logic;
1196  signal gt3_rxphmonitor_i : std_logic_vector(4 downto 0);
1197  signal gt3_rxphslipmonitor_i : std_logic_vector(4 downto 0);
1198  signal gt3_rxsyncallin_i : std_logic;
1199  signal gt3_rxsyncdone_i : std_logic;
1200  signal gt3_rxsyncin_i : std_logic;
1201  signal gt3_rxsyncmode_i : std_logic;
1202  signal gt3_rxsyncout_i : std_logic;
1203  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1204  signal gt3_rxbyteisaligned_i : std_logic;
1205  signal gt3_rxbyterealign_i : std_logic;
1206  signal gt3_rxcommadet_i : std_logic;
1207  --------------------- Receive Ports - RX Equalizer Ports -------------------
1208  signal gt3_rxdfeagchold_i : std_logic;
1209  signal gt3_rxdfelfhold_i : std_logic;
1210  signal gt3_rxmonitorout_i : std_logic_vector(6 downto 0);
1211  signal gt3_rxmonitorsel_i : std_logic_vector(1 downto 0);
1212  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1213  signal gt3_rxoutclk_i : std_logic;
1214  signal gt3_rxoutclkfabric_i : std_logic;
1215  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1216  signal gt3_gtrxreset_i : std_logic;
1217  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1218  signal gt3_rxchariscomma_i : std_logic_vector(3 downto 0);
1219  signal gt3_rxcharisk_i : std_logic_vector(3 downto 0);
1220  ------------------------ Receive Ports -RX AFE Ports -----------------------
1221  signal gt3_gthrxp_i : std_logic;
1222  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1223  signal gt3_rxresetdone_i : std_logic;
1224  --------------------- TX Initialization and Reset Ports --------------------
1225  signal gt3_gttxreset_i : std_logic;
1226  signal gt3_txuserrdy_i : std_logic;
1227  ------------------ Transmit Ports - TX Buffer Bypass Ports -----------------
1228  signal gt3_txdlyen_i : std_logic;
1229  signal gt3_txdlysreset_i : std_logic;
1230  signal gt3_txdlysresetdone_i : std_logic;
1231  signal gt3_txphalign_i : std_logic;
1232  signal gt3_txphaligndone_i : std_logic;
1233  signal gt3_txphalignen_i : std_logic;
1234  signal gt3_txphdlyreset_i : std_logic;
1235  signal gt3_txphinit_i : std_logic;
1236  signal gt3_txphinitdone_i : std_logic;
1237  ------------------ Transmit Ports - TX Data Path interface -----------------
1238  signal gt3_txdata_i : std_logic_vector(31 downto 0);
1239  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1240  signal gt3_gthtxn_i : std_logic;
1241  signal gt3_gthtxp_i : std_logic;
1242  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1243  signal gt3_txoutclk_i : std_logic;
1244  signal gt3_txoutclkfabric_i : std_logic;
1245  signal gt3_txoutclkpcs_i : std_logic;
1246  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1247  signal gt3_txresetdone_i : std_logic;
1248  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1249  signal gt3_txcharisk_i : std_logic_vector(3 downto 0);
1250 
1251  --____________________________COMMON PORTS________________________________
1252  signal gt0_qplllock_i : std_logic;
1253  signal gt0_qpllrefclklost_i : std_logic;
1254  signal gt0_qpllreset_i : std_logic;
1255  signal gt0_qpllreset_t : std_logic;
1256  signal gt0_qplloutclk_i : std_logic;
1257  signal gt0_qplloutrefclk_i : std_logic;
1258 
1259  ------------------------------- Global Signals -----------------------------
1260  signal gt0_tx_system_reset_c : std_logic;
1261  signal gt0_rx_system_reset_c : std_logic;
1262  signal gt1_tx_system_reset_c : std_logic;
1263  signal gt1_rx_system_reset_c : std_logic;
1264  signal gt2_tx_system_reset_c : std_logic;
1265  signal gt2_rx_system_reset_c : std_logic;
1266  signal gt3_tx_system_reset_c : std_logic;
1267  signal gt3_rx_system_reset_c : std_logic;
1268  signal tied_to_ground_i : std_logic;
1269  signal tied_to_ground_vec_i : std_logic_vector(63 downto 0);
1270  signal tied_to_vcc_i : std_logic;
1271  signal tied_to_vcc_vec_i : std_logic_vector(7 downto 0);
1272  signal drpclk_in_i : std_logic;
1273  signal sysclk_in_i : std_logic;
1274  signal GTTXRESET_IN : std_logic;
1275  signal GTRXRESET_IN : std_logic;
1276  signal QPLLRESET_IN : std_logic;
1277 
1278  attribute keep: string;
1279  ------------------------------- User Clocks ---------------------------------
1280  signal gt0_txusrclk_i : std_logic;
1281  signal gt0_txusrclk2_i : std_logic;
1282  signal gt0_rxusrclk_i : std_logic;
1283  signal gt0_rxusrclk2_i : std_logic;
1284 
1285 
1286 
1287 
1288  signal gt1_txusrclk_i : std_logic;
1289  signal gt1_txusrclk2_i : std_logic;
1290  signal gt1_rxusrclk_i : std_logic;
1291  signal gt1_rxusrclk2_i : std_logic;
1292 
1293 
1294 
1295 
1296  signal gt2_txusrclk_i : std_logic;
1297  signal gt2_txusrclk2_i : std_logic;
1298  signal gt2_rxusrclk_i : std_logic;
1299  signal gt2_rxusrclk2_i : std_logic;
1300 
1301 
1302 
1303 
1304  signal gt3_txusrclk_i : std_logic;
1305  signal gt3_txusrclk2_i : std_logic;
1306  signal gt3_rxusrclk_i : std_logic;
1307  signal gt3_rxusrclk2_i : std_logic;
1308 
1309 
1310 
1311 
1312  ----------------------------- Reference Clocks ----------------------------
1313 
1314 signal q1_clk1_refclk_i : std_logic;
1315  signal gt0_gtgrefclk_common_i : std_logic;
1316  signal gt0_gtnorthrefclk0_common_i : std_logic;
1317  signal gt0_gtnorthrefclk1_common_i : std_logic;
1318  signal gt0_gtrefclk1_common_i : std_logic;
1319  signal gt0_gtsouthrefclk0_common_i : std_logic;
1320  signal gt0_gtsouthrefclk1_common_i : std_logic;
1321 
1322 signal commonreset_i : std_logic;
1323 --**************************** Main Body of Code *******************************
1324 begin
1325 
1326  -- Static signal Assigments
1327 tied_to_ground_i <= '0';
1328 tied_to_ground_vec_i <= x"0000000000000000";
1329 tied_to_vcc_i <= '1';
1330 tied_to_vcc_vec_i <= "11111111";
1331 
1332 
1333  gt0_qplllock_out <= gt0_qplllock_i;
1334  gt0_qpllrefclklost_out <= gt0_qpllrefclklost_i;
1335  gt0_qpllreset_t <= commonreset_i or gt0_qpllreset_i;
1336  gt0_qplloutclk_out <= gt0_qplloutclk_i;
1337  gt0_qplloutrefclk_out <= gt0_qplloutrefclk_i;
1338 
1339 
1340 
1341  GT0_TXUSRCLK_OUT <= gt0_txusrclk_i;
1342  GT0_TXUSRCLK2_OUT <= gt0_txusrclk2_i;
1343  GT0_RXUSRCLK_OUT <= gt0_rxusrclk_i;
1344  GT0_RXUSRCLK2_OUT <= gt0_rxusrclk2_i;
1345 
1346  GT1_TXUSRCLK_OUT <= gt1_txusrclk_i;
1347  GT1_TXUSRCLK2_OUT <= gt1_txusrclk2_i;
1348  GT1_RXUSRCLK_OUT <= gt1_rxusrclk_i;
1349  GT1_RXUSRCLK2_OUT <= gt1_rxusrclk2_i;
1350 
1351  GT2_TXUSRCLK_OUT <= gt2_txusrclk_i;
1352  GT2_TXUSRCLK2_OUT <= gt2_txusrclk2_i;
1353  GT2_RXUSRCLK_OUT <= gt2_rxusrclk_i;
1354  GT2_RXUSRCLK2_OUT <= gt2_rxusrclk2_i;
1355 
1356  GT3_TXUSRCLK_OUT <= gt3_txusrclk_i;
1357  GT3_TXUSRCLK2_OUT <= gt3_txusrclk2_i;
1358  GT3_RXUSRCLK_OUT <= gt3_rxusrclk_i;
1359  GT3_RXUSRCLK2_OUT <= gt3_rxusrclk2_i;
1360 
1361 
1362 
1363 
1364 
1365 
1366 
1367 
1368 
1369 
1370  gt_usrclk_source : mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE
1371  port map
1372  (
1373 
1374  GT0_TXUSRCLK_OUT => gt0_txusrclk_i,
1375  GT0_TXUSRCLK2_OUT => gt0_txusrclk2_i,
1376  GT0_TXOUTCLK_IN => gt0_txoutclk_i,
1377  GT0_RXUSRCLK_OUT => gt0_rxusrclk_i,
1378  GT0_RXUSRCLK2_OUT => gt0_rxusrclk2_i,
1379  GT0_RXOUTCLK_IN => gt0_rxoutclk_i,
1380 
1381  GT1_TXUSRCLK_OUT => gt1_txusrclk_i,
1382  GT1_TXUSRCLK2_OUT => gt1_txusrclk2_i,
1383  GT1_TXOUTCLK_IN => gt1_txoutclk_i,
1384  GT1_RXUSRCLK_OUT => gt1_rxusrclk_i,
1385  GT1_RXUSRCLK2_OUT => gt1_rxusrclk2_i,
1386  GT1_RXOUTCLK_IN => gt1_rxoutclk_i,
1387 
1388  GT2_TXUSRCLK_OUT => gt2_txusrclk_i,
1389  GT2_TXUSRCLK2_OUT => gt2_txusrclk2_i,
1390  GT2_TXOUTCLK_IN => gt2_txoutclk_i,
1391  GT2_RXUSRCLK_OUT => gt2_rxusrclk_i,
1392  GT2_RXUSRCLK2_OUT => gt2_rxusrclk2_i,
1393  GT2_RXOUTCLK_IN => gt2_rxoutclk_i,
1394 
1395  GT3_TXUSRCLK_OUT => gt3_txusrclk_i,
1396  GT3_TXUSRCLK2_OUT => gt3_txusrclk2_i,
1397  GT3_TXOUTCLK_IN => gt3_txoutclk_i,
1398  GT3_RXUSRCLK_OUT => gt3_rxusrclk_i,
1399  GT3_RXUSRCLK2_OUT => gt3_rxusrclk2_i,
1400  GT3_RXOUTCLK_IN => gt3_rxoutclk_i,
1401  Q1_CLK1_GTREFCLK_PAD_N_IN => Q1_CLK1_GTREFCLK_PAD_N_IN,
1402  Q1_CLK1_GTREFCLK_PAD_P_IN => Q1_CLK1_GTREFCLK_PAD_P_IN,
1403  Q1_CLK1_GTREFCLK_OUT => q1_clk1_refclk_i
1404 
1405  );
1406 
1407 sysclk_in_i <= sysclk_in;
1408 
1409  common0_i:mgt11g2_tx_rx_cfpga_common
1410  generic map
1411  (
1412  WRAPPER_SIM_GTRESET_SPEEDUP => EXAMPLE_SIM_GTRESET_SPEEDUP,
1413  SIM_QPLLREFCLK_SEL => "010"
1414  )
1415  port map
1416  (
1417  GTGREFCLK_IN => gt0_gtgrefclk_common_i,
1418  GTNORTHREFCLK0_IN => gt0_gtnorthrefclk0_common_i,
1419  GTNORTHREFCLK1_IN => gt0_gtnorthrefclk1_common_i,
1420  GTSOUTHREFCLK0_IN => gt0_gtsouthrefclk0_common_i,
1421  GTSOUTHREFCLK1_IN => gt0_gtsouthrefclk1_common_i,
1422  QPLLREFCLKSEL_IN => "010",
1423  GTREFCLK0_IN => tied_to_ground_i,
1424  GTREFCLK1_IN => q1_clk1_refclk_i,
1425  QPLLLOCK_OUT => gt0_qplllock_i,
1426  QPLLLOCKDETCLK_IN => sysclk_in_i,
1427  QPLLOUTCLK_OUT => gt0_qplloutclk_i,
1428  QPLLOUTREFCLK_OUT => gt0_qplloutrefclk_i,
1429  QPLLREFCLKLOST_OUT => gt0_qpllrefclklost_i,
1430  QPLLRESET_IN => gt0_qpllreset_t
1431 
1432 );
1433 
1434  common_reset_i:mgt11g2_tx_rx_cfpga_common_reset
1435  generic map
1436  (
1437  STABLE_CLOCK_PERIOD =>STABLE_CLOCK_PERIOD -- Period of the stable clock driving this state-machine, unit is [ns]
1438  )
1439  port map
1440  (
1441  STABLE_CLOCK => sysclk_in_i, --Stable Clock, either a stable clock from the PCB
1442 
1443  SOFT_RESET => soft_reset_tx_in, --User Reset, can be pulled any time
1444  COMMON_RESET => commonreset_i --Reset QPLL
1445  );
1446 
1447 
1448  mgt11g2_tx_rx_cfpga_init_i : mgt11g2_tx_rx_cfpga
1449  port map
1450  (
1451  sysclk_in => sysclk_in_i,
1452  soft_reset_tx_in => SOFT_RESET_TX_IN,
1453  soft_reset_rx_in => SOFT_RESET_RX_IN,
1454  dont_reset_on_data_error_in => DONT_RESET_ON_DATA_ERROR_IN,
1455  gt0_tx_fsm_reset_done_out => gt0_tx_fsm_reset_done_out,
1456  gt0_rx_fsm_reset_done_out => gt0_rx_fsm_reset_done_out,
1457  gt0_data_valid_in => gt0_data_valid_in,
1458  gt1_tx_fsm_reset_done_out => gt1_tx_fsm_reset_done_out,
1459  gt1_rx_fsm_reset_done_out => gt1_rx_fsm_reset_done_out,
1460  gt1_data_valid_in => gt1_data_valid_in,
1461  gt2_tx_fsm_reset_done_out => gt2_tx_fsm_reset_done_out,
1462  gt2_rx_fsm_reset_done_out => gt2_rx_fsm_reset_done_out,
1463  gt2_data_valid_in => gt2_data_valid_in,
1464  gt3_tx_fsm_reset_done_out => gt3_tx_fsm_reset_done_out,
1465  gt3_rx_fsm_reset_done_out => gt3_rx_fsm_reset_done_out,
1466  gt3_data_valid_in => gt3_data_valid_in,
1467 
1468  --_____________________________________________________________________
1469  --_____________________________________________________________________
1470  --GT0 (X1Y4)
1471 
1472  -------------------------- Channel - Clocking Ports ------------------------
1473  gt0_gtnorthrefclk0_in => gt0_gtnorthrefclk0_in,
1474  gt0_gtnorthrefclk1_in => gt0_gtnorthrefclk1_in,
1475  gt0_gtsouthrefclk0_in => gt0_gtsouthrefclk0_in,
1476  gt0_gtsouthrefclk1_in => gt0_gtsouthrefclk1_in,
1477  ---------------------------- Channel - DRP Ports --------------------------
1478  gt0_drpaddr_in => gt0_drpaddr_in,
1479  gt0_drpclk_in => sysclk_in_i,
1480  gt0_drpdi_in => gt0_drpdi_in,
1481  gt0_drpdo_out => gt0_drpdo_out,
1482  gt0_drpen_in => gt0_drpen_in,
1483  gt0_drprdy_out => gt0_drprdy_out,
1484  gt0_drpwe_in => gt0_drpwe_in,
1485 
1486  ------------------------------ Power-Down Ports ----------------------------
1487  gt0_rxpd_in => gt0_rxpd_in,
1488  gt0_txpd_in => gt0_txpd_in,
1489  --------------------- RX Initialization and Reset Ports --------------------
1490  gt0_eyescanreset_in => gt0_eyescanreset_in,
1491  gt0_rxuserrdy_in => gt0_rxuserrdy_in,
1492  -------------------------- RX Margin Analysis Ports ------------------------
1493  gt0_eyescandataerror_out => gt0_eyescandataerror_out,
1494  gt0_eyescantrigger_in => gt0_eyescantrigger_in,
1495  ------------------- Receive Ports - Digital Monitor Ports ------------------
1496  gt0_dmonitorout_out => gt0_dmonitorout_out,
1497  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1498  gt0_rxusrclk_in => gt0_rxusrclk_i,
1499  gt0_rxusrclk2_in => gt0_rxusrclk2_i,
1500  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1501  gt0_rxdata_out => gt0_rxdata_out,
1502  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1503  gt0_rxdisperr_out => gt0_rxdisperr_out,
1504  gt0_rxnotintable_out => gt0_rxnotintable_out,
1505  ------------------------ Receive Ports - RX AFE Ports ----------------------
1506  gt0_gthrxn_in => gt0_gthrxn_in,
1507  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1508  gt0_rxphmonitor_out => gt0_rxphmonitor_out,
1509  gt0_rxphslipmonitor_out => gt0_rxphslipmonitor_out,
1510  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1511  gt0_rxbyteisaligned_out => gt0_rxbyteisaligned_out,
1512  gt0_rxbyterealign_out => gt0_rxbyterealign_out,
1513  gt0_rxcommadet_out => gt0_rxcommadet_out,
1514  --------------------- Receive Ports - RX Equalizer Ports -------------------
1515  gt0_rxmonitorout_out => gt0_rxmonitorout_out,
1516  gt0_rxmonitorsel_in => gt0_rxmonitorsel_in,
1517  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1518  gt0_rxoutclk_out => gt0_rxoutclk_i,
1519  gt0_rxoutclkfabric_out => gt0_rxoutclkfabric_out,
1520  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1521  gt0_gtrxreset_in => gt0_gtrxreset_in,
1522  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1523  gt0_rxchariscomma_out => gt0_rxchariscomma_out,
1524  gt0_rxcharisk_out => gt0_rxcharisk_out,
1525  ------------------------ Receive Ports -RX AFE Ports -----------------------
1526  gt0_gthrxp_in => gt0_gthrxp_in,
1527  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1528  gt0_rxresetdone_out => gt0_rxresetdone_out,
1529  --------------------- TX Initialization and Reset Ports --------------------
1530  gt0_gttxreset_in => gt0_gttxreset_in,
1531  gt0_txuserrdy_in => gt0_txuserrdy_in,
1532  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1533  gt0_txusrclk_in => gt0_txusrclk_i,
1534  gt0_txusrclk2_in => gt0_txusrclk2_i,
1535  ------------------ Transmit Ports - TX Data Path interface -----------------
1536  gt0_txdata_in => gt0_txdata_in,
1537  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1538  gt0_gthtxn_out => gt0_gthtxn_out,
1539  gt0_gthtxp_out => gt0_gthtxp_out,
1540  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1541  gt0_txoutclk_out => gt0_txoutclk_i,
1542  gt0_txoutclkfabric_out => gt0_txoutclkfabric_out,
1543  gt0_txoutclkpcs_out => gt0_txoutclkpcs_out,
1544  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1545  gt0_txresetdone_out => gt0_txresetdone_out,
1546  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1547  gt0_txcharisk_in => gt0_txcharisk_in,
1548 
1549  --_____________________________________________________________________
1550  --_____________________________________________________________________
1551  --GT1 (X1Y5)
1552 
1553  -------------------------- Channel - Clocking Ports ------------------------
1554  gt1_gtnorthrefclk0_in => gt1_gtnorthrefclk0_in,
1555  gt1_gtnorthrefclk1_in => gt1_gtnorthrefclk1_in,
1556  gt1_gtsouthrefclk0_in => gt1_gtsouthrefclk0_in,
1557  gt1_gtsouthrefclk1_in => gt1_gtsouthrefclk1_in,
1558  ---------------------------- Channel - DRP Ports --------------------------
1559  gt1_drpaddr_in => gt1_drpaddr_in,
1560  gt1_drpclk_in => sysclk_in_i,
1561  gt1_drpdi_in => gt1_drpdi_in,
1562  gt1_drpdo_out => gt1_drpdo_out,
1563  gt1_drpen_in => gt1_drpen_in,
1564  gt1_drprdy_out => gt1_drprdy_out,
1565  gt1_drpwe_in => gt1_drpwe_in,
1566  ------------------------------ Power-Down Ports ----------------------------
1567  gt1_rxpd_in => gt1_rxpd_in,
1568  gt1_txpd_in => gt1_txpd_in,
1569  --------------------- RX Initialization and Reset Ports --------------------
1570  gt1_eyescanreset_in => gt1_eyescanreset_in,
1571  gt1_rxuserrdy_in => gt1_rxuserrdy_in,
1572  -------------------------- RX Margin Analysis Ports ------------------------
1573  gt1_eyescandataerror_out => gt1_eyescandataerror_out,
1574  gt1_eyescantrigger_in => gt1_eyescantrigger_in,
1575  ------------------- Receive Ports - Digital Monitor Ports ------------------
1576  gt1_dmonitorout_out => gt1_dmonitorout_out,
1577  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1578  gt1_rxusrclk_in => gt1_rxusrclk_i,
1579  gt1_rxusrclk2_in => gt1_rxusrclk2_i,
1580  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1581  gt1_rxdata_out => gt1_rxdata_out,
1582  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1583  gt1_rxdisperr_out => gt1_rxdisperr_out,
1584  gt1_rxnotintable_out => gt1_rxnotintable_out,
1585  ------------------------ Receive Ports - RX AFE Ports ----------------------
1586  gt1_gthrxn_in => gt1_gthrxn_in,
1587  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1588  gt1_rxphmonitor_out => gt1_rxphmonitor_out,
1589  gt1_rxphslipmonitor_out => gt1_rxphslipmonitor_out,
1590  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1591  gt1_rxbyteisaligned_out => gt1_rxbyteisaligned_out,
1592  gt1_rxbyterealign_out => gt1_rxbyterealign_out,
1593  gt1_rxcommadet_out => gt1_rxcommadet_out,
1594  --------------------- Receive Ports - RX Equalizer Ports -------------------
1595  gt1_rxmonitorout_out => gt1_rxmonitorout_out,
1596  gt1_rxmonitorsel_in => gt1_rxmonitorsel_in,
1597  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1598  gt1_rxoutclk_out => gt1_rxoutclk_i,
1599  gt1_rxoutclkfabric_out => gt1_rxoutclkfabric_out,
1600  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1601  gt1_gtrxreset_in => gt1_gtrxreset_in,
1602  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1603  gt1_rxchariscomma_out => gt1_rxchariscomma_out,
1604  gt1_rxcharisk_out => gt1_rxcharisk_out,
1605  ------------------------ Receive Ports -RX AFE Ports -----------------------
1606  gt1_gthrxp_in => gt1_gthrxp_in,
1607  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1608  gt1_rxresetdone_out => gt1_rxresetdone_out,
1609  --------------------- TX Initialization and Reset Ports --------------------
1610  gt1_gttxreset_in => gt1_gttxreset_in,
1611  gt1_txuserrdy_in => gt1_txuserrdy_in,
1612  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1613  gt1_txusrclk_in => gt1_txusrclk_i,
1614  gt1_txusrclk2_in => gt1_txusrclk2_i,
1615  ------------------ Transmit Ports - TX Data Path interface -----------------
1616  gt1_txdata_in => gt1_txdata_in,
1617  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1618  gt1_gthtxn_out => gt1_gthtxn_out,
1619  gt1_gthtxp_out => gt1_gthtxp_out,
1620  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1621  gt1_txoutclk_out => gt1_txoutclk_i,
1622  gt1_txoutclkfabric_out => gt1_txoutclkfabric_out,
1623  gt1_txoutclkpcs_out => gt1_txoutclkpcs_out,
1624  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1625  gt1_txresetdone_out => gt1_txresetdone_out,
1626  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1627  gt1_txcharisk_in => gt1_txcharisk_in,
1628 
1629 
1630 
1631  --_____________________________________________________________________
1632  --_____________________________________________________________________
1633  --GT2 (X1Y6)
1634 
1635  -------------------------- Channel - Clocking Ports ------------------------
1636  gt2_gtnorthrefclk0_in => gt2_gtnorthrefclk0_in,
1637  gt2_gtnorthrefclk1_in => gt2_gtnorthrefclk1_in,
1638  gt2_gtsouthrefclk0_in => gt2_gtsouthrefclk0_in,
1639  gt2_gtsouthrefclk1_in => gt2_gtsouthrefclk1_in,
1640  ---------------------------- Channel - DRP Ports --------------------------
1641  gt2_drpaddr_in => gt2_drpaddr_in,
1642  gt2_drpclk_in => sysclk_in_i,
1643  gt2_drpdi_in => gt2_drpdi_in,
1644  gt2_drpdo_out => gt2_drpdo_out,
1645  gt2_drpen_in => gt2_drpen_in,
1646  gt2_drprdy_out => gt2_drprdy_out,
1647  gt2_drpwe_in => gt2_drpwe_in,
1648  ------------------------------ Power-Down Ports ----------------------------
1649  gt2_rxpd_in => gt2_rxpd_in,
1650  gt2_txpd_in => gt2_txpd_in,
1651  --------------------- RX Initialization and Reset Ports --------------------
1652  gt2_eyescanreset_in => gt2_eyescanreset_in,
1653  gt2_rxuserrdy_in => gt2_rxuserrdy_in,
1654  -------------------------- RX Margin Analysis Ports ------------------------
1655  gt2_eyescandataerror_out => gt2_eyescandataerror_out,
1656  gt2_eyescantrigger_in => gt2_eyescantrigger_in,
1657  ------------------- Receive Ports - Digital Monitor Ports ------------------
1658  gt2_dmonitorout_out => gt2_dmonitorout_out,
1659  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1660  gt2_rxusrclk_in => gt2_rxusrclk_i,
1661  gt2_rxusrclk2_in => gt2_rxusrclk2_i,
1662  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1663  gt2_rxdata_out => gt2_rxdata_out,
1664  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1665  gt2_rxdisperr_out => gt2_rxdisperr_out,
1666  gt2_rxnotintable_out => gt2_rxnotintable_out,
1667  ------------------------ Receive Ports - RX AFE Ports ----------------------
1668  gt2_gthrxn_in => gt2_gthrxn_in,
1669  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1670  gt2_rxphmonitor_out => gt2_rxphmonitor_out,
1671  gt2_rxphslipmonitor_out => gt2_rxphslipmonitor_out,
1672  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1673  gt2_rxbyteisaligned_out => gt2_rxbyteisaligned_out,
1674  gt2_rxbyterealign_out => gt2_rxbyterealign_out,
1675  gt2_rxcommadet_out => gt2_rxcommadet_out,
1676  --------------------- Receive Ports - RX Equalizer Ports -------------------
1677  gt2_rxmonitorout_out => gt2_rxmonitorout_out,
1678  gt2_rxmonitorsel_in => gt2_rxmonitorsel_in,
1679  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1680  gt2_rxoutclk_out => gt2_rxoutclk_i,
1681  gt2_rxoutclkfabric_out => gt2_rxoutclkfabric_out,
1682  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1683  gt2_gtrxreset_in => gt2_gtrxreset_in,
1684  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1685  gt2_rxchariscomma_out => gt2_rxchariscomma_out,
1686  gt2_rxcharisk_out => gt2_rxcharisk_out,
1687  ------------------------ Receive Ports -RX AFE Ports -----------------------
1688  gt2_gthrxp_in => gt2_gthrxp_in,
1689  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1690  gt2_rxresetdone_out => gt2_rxresetdone_out,
1691  --------------------- TX Initialization and Reset Ports --------------------
1692  gt2_gttxreset_in => gt2_gttxreset_in,
1693  gt2_txuserrdy_in => gt2_txuserrdy_in,
1694  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1695  gt2_txusrclk_in => gt2_txusrclk_i,
1696  gt2_txusrclk2_in => gt2_txusrclk2_i,
1697  ------------------ Transmit Ports - TX Data Path interface -----------------
1698  gt2_txdata_in => gt2_txdata_in,
1699  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1700  gt2_gthtxn_out => gt2_gthtxn_out,
1701  gt2_gthtxp_out => gt2_gthtxp_out,
1702  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1703  gt2_txoutclk_out => gt2_txoutclk_i,
1704  gt2_txoutclkfabric_out => gt2_txoutclkfabric_out,
1705  gt2_txoutclkpcs_out => gt2_txoutclkpcs_out,
1706  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1707  gt2_txresetdone_out => gt2_txresetdone_out,
1708  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1709  gt2_txcharisk_in => gt2_txcharisk_in,
1710 
1711  --_____________________________________________________________________
1712  --_____________________________________________________________________
1713  --GT3 (X1Y7)
1714 
1715  -------------------------- Channel - Clocking Ports ------------------------
1716  gt3_gtnorthrefclk0_in => gt3_gtnorthrefclk0_in,
1717  gt3_gtnorthrefclk1_in => gt3_gtnorthrefclk1_in,
1718  gt3_gtsouthrefclk0_in => gt3_gtsouthrefclk0_in,
1719  gt3_gtsouthrefclk1_in => gt3_gtsouthrefclk1_in,
1720  ---------------------------- Channel - DRP Ports --------------------------
1721  gt3_drpaddr_in => gt3_drpaddr_in,
1722  gt3_drpclk_in => sysclk_in_i,
1723  gt3_drpdi_in => gt3_drpdi_in,
1724  gt3_drpdo_out => gt3_drpdo_out,
1725  gt3_drpen_in => gt3_drpen_in,
1726  gt3_drprdy_out => gt3_drprdy_out,
1727  gt3_drpwe_in => gt3_drpwe_in,
1728  ------------------------------ Power-Down Ports ----------------------------
1729  gt3_rxpd_in => gt3_rxpd_in,
1730  gt3_txpd_in => gt3_txpd_in,
1731  --------------------- RX Initialization and Reset Ports --------------------
1732  gt3_eyescanreset_in => gt3_eyescanreset_in,
1733  gt3_rxuserrdy_in => gt3_rxuserrdy_in,
1734  -------------------------- RX Margin Analysis Ports ------------------------
1735  gt3_eyescandataerror_out => gt3_eyescandataerror_out,
1736  gt3_eyescantrigger_in => gt3_eyescantrigger_in,
1737  ------------------- Receive Ports - Digital Monitor Ports ------------------
1738  gt3_dmonitorout_out => gt3_dmonitorout_out,
1739  ------------------ Receive Ports - FPGA RX Interface Ports -----------------
1740  gt3_rxusrclk_in => gt3_rxusrclk_i,
1741  gt3_rxusrclk2_in => gt3_rxusrclk2_i,
1742  ------------------ Receive Ports - FPGA RX interface Ports -----------------
1743  gt3_rxdata_out => gt3_rxdata_out,
1744  ------------------ Receive Ports - RX 8B/10B Decoder Ports -----------------
1745  gt3_rxdisperr_out => gt3_rxdisperr_out,
1746  gt3_rxnotintable_out => gt3_rxnotintable_out,
1747  ------------------------ Receive Ports - RX AFE Ports ----------------------
1748  gt3_gthrxn_in => gt3_gthrxn_in,
1749  ------------------- Receive Ports - RX Buffer Bypass Ports -----------------
1750  gt3_rxphmonitor_out => gt3_rxphmonitor_out,
1751  gt3_rxphslipmonitor_out => gt3_rxphslipmonitor_out,
1752  -------------- Receive Ports - RX Byte and Word Alignment Ports ------------
1753  gt3_rxbyteisaligned_out => gt3_rxbyteisaligned_out,
1754  gt3_rxbyterealign_out => gt3_rxbyterealign_out,
1755  gt3_rxcommadet_out => gt3_rxcommadet_out,
1756  --------------------- Receive Ports - RX Equalizer Ports -------------------
1757  gt3_rxmonitorout_out => gt3_rxmonitorout_out,
1758  gt3_rxmonitorsel_in => gt3_rxmonitorsel_in,
1759  --------------- Receive Ports - RX Fabric Output Control Ports -------------
1760  gt3_rxoutclk_out => gt3_rxoutclk_i,
1761  gt3_rxoutclkfabric_out => gt3_rxoutclkfabric_out,
1762  ------------- Receive Ports - RX Initialization and Reset Ports ------------
1763  gt3_gtrxreset_in => gt3_gtrxreset_in,
1764  ------------------- Receive Ports - RX8B/10B Decoder Ports -----------------
1765  gt3_rxchariscomma_out => gt3_rxchariscomma_out,
1766  gt3_rxcharisk_out => gt3_rxcharisk_out,
1767  ------------------------ Receive Ports -RX AFE Ports -----------------------
1768  gt3_gthrxp_in => gt3_gthrxp_in,
1769  -------------- Receive Ports -RX Initialization and Reset Ports ------------
1770  gt3_rxresetdone_out => gt3_rxresetdone_out,
1771  --------------------- TX Initialization and Reset Ports --------------------
1772  gt3_gttxreset_in => gt3_gttxreset_in,
1773  gt3_txuserrdy_in => gt3_txuserrdy_in,
1774  ------------------ Transmit Ports - FPGA TX Interface Ports ----------------
1775  gt3_txusrclk_in => gt3_txusrclk_i,
1776  gt3_txusrclk2_in => gt3_txusrclk2_i,
1777  ------------------ Transmit Ports - TX Data Path interface -----------------
1778  gt3_txdata_in => gt3_txdata_in,
1779  ---------------- Transmit Ports - TX Driver and OOB signaling --------------
1780  gt3_gthtxn_out => gt3_gthtxn_out,
1781  gt3_gthtxp_out => gt3_gthtxp_out,
1782  ----------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
1783  gt3_txoutclk_out => gt3_txoutclk_i,
1784  gt3_txoutclkfabric_out => gt3_txoutclkfabric_out,
1785  gt3_txoutclkpcs_out => gt3_txoutclkpcs_out,
1786  ------------- Transmit Ports - TX Initialization and Reset Ports -----------
1787  gt3_txresetdone_out => gt3_txresetdone_out,
1788  ----------- Transmit Transmit Ports - 8b10b Encoder Control Ports ----------
1789  gt3_txcharisk_in => gt3_txcharisk_in,
1790 
1791 
1792 
1793  gt0_qplllock_in => gt0_qplllock_i,
1794  gt0_qpllrefclklost_in => gt0_qpllrefclklost_i,
1795  gt0_qpllreset_out => gt0_qpllreset_i,
1796  gt0_qplloutclk_in => gt0_qplloutclk_i,
1797  gt0_qplloutrefclk_in => gt0_qplloutrefclk_i
1798  );
1799 
1800 
1801 
1802 end RTL;
1803 
mgt11g2_tx_rx_cfpga_GT_USRCLK_SOURCE
Definition: mgt11g2_tx_rx_cfpga_gt_usrclk_source.vhd:72
mgt11g2_tx_rx_cfpga_common_reset
Definition: mgt11g2_tx_rx_cfpga_common_reset.vhd:78
mgt11g2_tx_rx_cfpga_common
Definition: mgt11g2_tx_rx_cfpga_common.vhd:70
mgt11g2_tx_rx_cfpga_support.RTL
Definition: mgt11g2_tx_rx_cfpga_support.vhd:410
mgt11g2_tx_rx_cfpga_support
Definition: mgt11g2_tx_rx_cfpga_support.vhd:74
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