eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

Back to eFEX documentation
top_efex_control.vhd
Go to the documentation of this file.
1 
53 
54 library ieee;
55 use ieee.std_logic_1164.all;
56 use ieee.numeric_std.all;
57 library ipbus_lib;
58 use ipbus_lib.ipbus.all;
59 library unisim;
60 use unisim.VComponents.all;
61 library infrastructure_lib;
62 use infrastructure_lib.all;
63 use infrastructure_lib.mgt_type.all;
64 use infrastructure_lib.ProcessorFPGAPackage.all;
65 use infrastructure_lib.ipbus_decode_L1CaloEfex.all;
66 use infrastructure_lib.packet_mux_type.all;
67 use infrastructure_lib.golden.all;
68 
70 entity top_efex_control is
71  generic (
73  FLAVOUR : integer := 0;
75  GLOBAL_DATE : std_logic_vector(31 downto 0) := x"00000000";
77  GLOBAL_TIME : std_logic_vector(31 downto 0) := x"00000000";
79  GLOBAL_SHA : std_logic_vector(31 downto 0) := x"00000000";
81  GLOBAL_VER : std_logic_vector(31 downto 0) := x"00000000";
82 
84  XML_SHA : std_logic_vector(31 downto 0) := x"00000000";
86  XML_VER : std_logic_vector(31 downto 0) := x"00000000";
87 
89  TOP_SHA : std_logic_vector(31 downto 0) := x"00000000";
91  TOP_VER : std_logic_vector(31 downto 0) := x"00000000";
92 
94  HOG_SHA : std_logic_vector(31 downto 0) := x"00000000";
95  HOG_VER : std_logic_vector(31 downto 0) := x"00000000";
96 
98  CON_SHA : std_logic_vector(31 downto 0) := x"00000000";
99  CON_VER : std_logic_vector(31 downto 0) := x"00000000";
100 
102  INFRASTRUCTURE_LIB_VER : std_logic_vector(31 downto 0) := x"00000000";
104  INFRASTRUCTURE_LIB_SHA : std_logic_vector(31 downto 0) := x"00000000";
106  IPBUS_LIB_SHA : std_logic_vector(31 downto 0) := x"00000000";
108  IPBUS_LIB_VER : std_logic_vector(31 downto 0) := x"00000000";
110  N_PROCESSORFPGA : positive := 4;
111  GOLDEN : boolean := false
112  );
113 
114  port(
115  gt_clk125_p : in std_logic;
116  gt_clk125_n : in std_logic;
117  gmii_gtx_clk : out std_logic;
118  gmii_tx_en : out std_logic;
119  gmii_tx_er : out std_logic;
120  gmii_txd : out std_logic_vector(7 downto 0);
121  gmii_rx_clk : in std_logic;
122  gmii_rx_dv : in std_logic;
123  gmii_rx_er : in std_logic;
124  gmii_rxd : in std_logic_vector(7 downto 0);
125  phy_rstb : out std_logic;
126  clk_40_n : in std_logic;
127  clk_40_p : in std_logic;
128  --------------------I2C connections
129  i2c_scl : out std_logic;
130  i2c_sda : inout std_logic;
131  i2c_rst_0 : out std_logic;
132  ------Pll connections-----
133  pll_miso : in std_logic;
134  pll_le_1 : out std_logic;
135  pll_le_3 : out std_logic;
136  pll_clko : out std_logic;
137  pll_mosi : out std_logic;
138  pll_lock_1 : in std_logic;
139  pll_lock_3 : in std_logic;
140  -------------Flash--------------
141  flash_csn : out std_logic;
142  flash_mosi : out std_logic;
143  flash_miso : in std_logic;
144  xtal_ttc_clk_sel : out std_logic;
145  SYNC_B_CDCE : out std_logic;
146  POWERDN_B_CDCE : out std_logic;
147  -- Signals coming to contrl FPGA
148  master_tx_data1 : in std_logic_vector (9 downto 0);
149  master_tx_data2 : in std_logic_vector (9 downto 0);
150  master_tx_data3 : in std_logic_vector (9 downto 0);
151  master_tx_data4 : in std_logic_vector (9 downto 0);
152  -- signals going out of cntrl FPGA
153  master_rx_data1 : out std_logic_vector (9 downto 0);
154  master_rx_data2 : out std_logic_vector (9 downto 0);
155  master_rx_data3 : out std_logic_vector (9 downto 0);
156  master_rx_data4 : out std_logic_vector (9 downto 0);
157  master_tx_pause1 : out std_logic;
158  master_tx_pause2 : out std_logic;
159  master_tx_pause3 : out std_logic;
160  master_tx_pause4 : out std_logic;
161  hardware_addr : in std_logic_vector(11 downto 0);
162  -------------- LEDs --------------
163  f5_ipbus_access_led : out std_logic;
164  f5_user_led_1 : out std_logic;
165  f5_ttc_clk_sel : out std_logic;
166  fifos_full : out std_logic := '0';
167  l1a_stretch : out std_logic := '0';
168  fpga1_done : in std_logic;
169  fpga2_done : in std_logic;
170  fpga3_done : in std_logic;
171  fpga4_done : in std_logic;
172  serial_number : in std_logic_vector(5 downto 0);
173  reset_clk125 : out std_logic_vector (3 downto 0);
174  VAUXP, VAUXN : in std_logic_vector (5 downto 0);
175  Vp, Vn : in std_logic;
176  ctrl_out : out efex_control_output;
177  ctrl_in : in efex_control_input
178  );
179 end top_efex_control;
180 
182 architecture spec of top_efex_control is
183 ------------------- chipscope for debuging
184  component ila_0
185  port (
186  clk : in std_logic;
187  probe0 : in std_logic_vector(69 downto 0)
188  );
189  end component ila_0;
190 
191  component ila_1
192  port (
193  clk : in std_logic;
194  probe0 : in std_logic_vector(34 downto 0)
195  );
196  end component ila_1;
197 
198  component clk_ttc is
199  port (
200  clk40 : out std_logic;
201  clk320 : out std_logic;
202  clk160 : out std_logic;
203  locked : out std_logic;
204  clk_in1_p : in std_logic;
205  clk_in1_n : in std_logic
206  );
207 
208  end component clk_ttc;
209 
210  component axi_stream_fifo is
211  port (
212  wr_rst_busy : out std_logic;
213  rd_rst_busy : out std_logic;
214  m_aclk : in std_logic;
215  s_aclk : in std_logic;
216  s_aresetn : in std_logic;
217  s_axis_tvalid : in std_logic;
218  s_axis_tready : out std_logic;
219  s_axis_tdata : in std_logic_vector (63 downto 0);
220  s_axis_tkeep : in std_logic_vector (7 downto 0);
221  s_axis_tlast : in std_logic;
222  s_axis_tuser : in std_logic_vector (3 downto 0);
223  m_axis_tvalid : out std_logic;
224  m_axis_tready : in std_logic;
225  m_axis_tdata : out std_logic_vector (63 downto 0);
226  m_axis_tkeep : out std_logic_vector (7 downto 0);
227  m_axis_tlast : out std_logic;
228  m_axis_tuser : out std_logic_vector (3 downto 0)
229  );
230  end component axi_stream_fifo;
231 
232 
233  -- Architecture declarations
234 
235  -- Phase-I: ttc_L1ID & ttc_ECRID & ttc_pr_rdout & ttc_ECR & ttc_BCR & ttc_L1A
236  -- Phase-II: ttc_L0ID & ttc_pr_rdout & ttc_TS & ttc_L0A
237  type ttc_delay_array is array(natural range <>) of std_logic_vector(40 downto 0);
238  --
239  signal efex_number : std_logic_vector(3 downto 0);
240  -- ipbus signals
241  signal clk125_fr, clk200, clk320, clk160, clko_p40, ipb_clk, mac_clk, clk_locked, eth_locked, clk40, clk280 : std_logic;
242  signal rx_clk280 : std_logic_vector(7 downto 0);
243  signal rst_125, rst_ipb, rst_eth, rst_macclk, sys_rst, soft_rst, rsto_eth, enable_pll_rst : std_logic;
244  signal reset_phy: std_logic := '1';
245  signal pseudo_orbit : std_logic;
246  signal mac_rx_data : std_logic_vector(7 downto 0);
247  signal mac_rx_error, mac_rx_valid, mac_rx_last, my_rx_error : std_logic;
248  signal force_rx_error_buf : std_logic_vector(1 downto 0) := (Others => '0');
249  signal mac_tx_data : std_logic_vector(7 downto 0);
250  signal mac_tx_error, mac_tx_last, mac_tx_ready, mac_tx_valid : std_logic;
251  signal onehz, nuke, rst_ipb_ctrl, got_ip_address : std_logic;
252  signal ipb_master_out : ipb_wbus;
253  signal ipb_master_in : ipb_rbus;
254  signal ipbw : ipb_wbus_array(N_SLAVES-1 downto 0);
255  signal ipbr, ipbr_d : ipb_rbus_array(N_SLAVES-1 downto 0);
256  signal ipb_in : ipb_rbus;
257  signal ipb_out : ipb_wbus;
258  signal master_rx_data1_int, master_rx_data2_int, master_rx_data3_int, master_rx_data4_int : std_logic_vector(8 downto 0);
259  signal master_tx_data1_int, master_tx_data2_int, master_tx_data3_int, master_tx_data4_int : std_logic_vector(8 downto 0);
260  signal flash_clk, flash_led, scl_enb_0, sda_enb_0, scl_enb_1, sda_enb_1, scl_o_0, sda_o_0, scl_o_1, sda_o_1 : std_logic;
261  signal Module_ID, status : std_logic_vector(31 downto 0);
262  signal master_tx_err1, master_tx_err2, master_tx_err3, master_tx_err4 : std_logic;
263  -----------------------------------------------------------------------------------------------------
264  signal control_reg, pulse_reg, reconfig_reg, last_input_data_l1id, input_data_readout_control : std_logic_vector (31 downto 0);
265  signal clkfb_in, gmii_rx_clk_int, clkfb_out : std_logic;
266  signal select_pll, select_flash : std_logic_vector (1 downto 0);
267  signal pll_en, flash_csn_int, trigger_reconfig, reconfig, en_reset : std_logic;
268  signal data_reg0, data_reg1, reg128_latch : std_logic;
269  signal flash_addr_int : std_logic_vector(2 downto 0);
270  signal flash_mosi_int, f5_flash_disable_int, f5_flash_csn_int : std_logic;
271  signal f1_flash_sel_int, f2_flash_sel_int, f3_flash_sel_int, f4_flash_sel_int : std_logic;
272  signal probe : std_logic_vector(12 downto 0);
273  signal start : std_logic;
274  -- mgt signals
275  signal hub1_rx_data, hub2_rx_data : std_logic_vector(31 downto 0);
276  signal rx_er_count : std_logic_vector(31 downto 0);
277  signal hub1_combined_ttc_rxclk, hub1_combined_ttc, hub1_combined_ttc_i, hub1_combined_ttc_ila : std_logic_vector(128 downto 0);
278  signal hub2_combined_ttc_rxclk, hub2_combined_ttc, hub2_combined_ttc_i, hub2_combined_ttc_ila : std_logic_vector(128 downto 0);
279  signal hub1_combined_ttc_valid, hub2_combined_ttc_valid : std_logic;
280  signal mgt_enable : std_logic_vector(3 downto 0);
281  signal bc_reg_sel, mux_sel : std_logic_vector(15 downto 0);
282  signal delay_cntr_0, delay_cntr_1 : std_logic_vector(3 downto 0);
283  signal rx_resetdone_mgt114 : std_logic_vector (1 downto 0);
284  signal mgt_commadret : std_logic_vector (1 downto 0);
285  signal rx_clk160 : std_logic_vector(3 downto 0);
286  signal RXN_IN_i, RXP_IN_i : std_logic_vector(11 downto 0);
287  signal encode_114, rx_disperr_114 : std_logic_vector(3 downto 0);
288  signal ttc_BCR, ttc_L1A, ttc_ECR, ttc_pr_rdout : std_logic;
289  signal ttc_ECRID : std_logic_vector(7 downto 0);
290  signal ttc_L1ID : std_logic_vector(23 downto 0);
291  signal sof_topo_fpga1, sof_topo_fpga2, sof_topo_fpga3, sof_topo_fpga4 : std_logic;
292  signal sof_raw_fpga1, sof_raw_fpga2, sof_raw_fpga3, sof_raw_fpga4 : std_logic;
293  signal rx_resetdone, tx_resetdone, tx_fsm_resetdone, rx_fsm_resetdone, rx_realign, rx_byteisaligned : std_logic_vector(11 downto 0);
294  signal loopback : std_logic_vector (5 downto 0);
295  signal rx_disperr, encode_error : std_logic_vector(47 downto 0);
296  signal qpll_lock, qpll_refclklost, softreset_tx, softreset_rx : std_logic_vector(2 downto 0);
297  signal tx_bufstatus : std_logic_vector(23 downto 0);
298  signal gmii_rx_er_i, hub2_combined_ttc_latch, link_reset_hub1, link_reset_hub2, ttc_fifo_reset : std_logic;
299  signal locked: std_logic := '0'; -- ensure initial conditions for master reset
300  signal reset: std_logic := '1'; -- ensure initial conditions for master reset
301 
302 ---Aurora hub1 signal declarations
303  signal s_axi_tx_tdata_hub1, s_axi_tx_tdata_data_hub1, s_axi_tx_tdata_ufc_hub1 : std_logic_vector (63 downto 0);
304  signal s_axi_tx_tvalid_hub1, s_axi_tx_tready_hub1, s_axi_tx_tready_vld_hub1, s_axi_tx_tlast_hub1 : std_logic;
305  signal s_axi_tx_tkeep_hub1 : std_logic_vector (7 downto 0);
306  signal s_axi_ufc_tx_req_hub1, s_axi_ufc_tx_ack_hub1 : std_logic;
307  signal s_axi_ufc_tx_ms_hub1 : std_logic_vector (2 downto 0);
308  signal aurora_status_hub1 : std_logic_vector(31 downto 0);
309  signal tx_lane_up_hub1 : std_logic_vector (3 downto 0);
310  signal tx_channel_up_hub1, tx_hard_err_hub1, tx_lock_hub1, pll_not_locked_hub1, aurora_tx_resetdone_hub1 : std_logic;
311  signal aurora_user_clk_hub1, sys_reset_out_hub1, init_clk_out_hub1, rd_rst_busy_hub1 : std_logic;
312  signal busy_status_hub1 : std_logic_vector (15 downto 0);
313 
314 ---Aurora hub2 signal declarations
315  signal s_axi_tx_tdata_hub2, s_axi_tx_tdata_data_hub2, s_axi_tx_tdata_ufc_hub2 : std_logic_vector (63 downto 0);
316  signal s_axi_tx_tvalid_hub2, s_axi_tx_tready_hub2, s_axi_tx_tready_vld_hub2, s_axi_tx_tlast_hub2 : std_logic;
317  signal s_axi_tx_tkeep_hub2 : std_logic_vector (7 downto 0);
318  signal s_axi_ufc_tx_req_hub2, s_axi_ufc_tx_ack_hub2 : std_logic;
319  signal s_axi_ufc_tx_ms_hub2 : std_logic_vector (2 downto 0);
320  signal aurora_status_hub2 : std_logic_vector(31 downto 0);
321  signal tx_lane_up_hub2 : std_logic_vector (3 downto 0);
322  signal tx_channel_up_hub2, tx_hard_err_hub2, tx_lock_hub2, pll_not_locked_hub2, aurora_tx_resetdone_hub2 : std_logic;
323  signal aurora_user_clk_hub2, sys_reset_out_hub2, init_clk_out_hub2, rd_rst_busy_hub2 : std_logic;
324  signal busy_status_hub2 : std_logic_vector (15 downto 0);
325 
326  signal payload_data : std_logic_vector(63 downto 0);
327  signal payload_valid, payload_last, tready_data, first : std_logic;
328  signal master_link_down_int, master_link_down_dly : std_logic_vector(3 downto 0);
329  signal fifo_empty, valid, rst_320, rst_320_n : std_logic;
330  signal bcn_cntr, BCN : std_logic_vector (11 downto 0);
331 
332 -- Readout signals
333  signal ttc_din : std_logic_vector(49 downto 0);
334  signal priv_rdout_l1id : std_logic_vector(23 downto 0);
335  signal priv_rdout_reg_1, priv_rdout_reg_2 : std_logic;
336 -- data from MGT
337  signal clk_mgt_bus : std_logic_vector(N_PROCESSORFPGA*2 - 1 downto 0);
338  signal data_from_mgt_bus : mgt_data_array(N_PROCESSORFPGA*2 - 1 downto 0);
339  signal char_is_k_bus : std_logic_vector(N_PROCESSORFPGA*2 - 1 downto 0);
340  signal error_from_mgt_bus : std_logic_vector(N_PROCESSORFPGA*2 - 1 downto 0);
341 -- data to Aurora FIFOs
342  signal payload_data_bus : packet_data_array(1 downto 0);
343  signal payload_valid_bus : std_logic_vector(1 downto 0);
344  signal payload_last_bus : std_logic_vector(1 downto 0);
345  signal tready_data_bus : std_logic_vector(1 downto 0);
346 -- flow control
347  signal tob_xoff_bus : std_logic_vector(1 downto 0);
348  signal raw_xoff_bus : std_logic_vector(1 downto 0);
349  signal mgt_xoff_bus, merged_busy_bus, processor_busy_bus, local_busy_bus: std_logic_vector(N_PROCESSORFPGA*2 - 1 downto 0) := (Others => '0'); -- in Processor Number order, (3 downto 0) TOBs (7 downto 4) Input Data
350 
351  signal packet_mux_source : std_logic_vector(7 downto 0);
352 
353  signal TXN_OUT_i, TXP_OUT_i : std_logic_vector(11 downto 0);
354  signal ftm_ttc_mode, phase2_ttc_mode : std_logic;
355  signal phase2_ttc_delay_offset : std_logic_vector(1 downto 0);
356  signal d_i, e_i, f_i, g_i, q_i : std_logic_vector (35 downto 0); -- 24 + 8 + 4
357  signal ttc_l1A_i, ttc_bcr_i, ttc_ecr_i, ttc_pr_rdout_i, ttc_parity_i : std_logic_vector(3 downto 0);
358  signal ttc_dummy_i : std_logic_vector (23 downto 0) := (Others => '0'); -- 4*(5 downto 0)
359  signal ttc_ECRID_i : std_logic_vector (31 downto 0); -- 4*(7 downto 0)
360  signal ttc_L1ID_i : std_logic_vector (95 downto 0); -- 4*(23 downto 0)
361  signal ttc_rst_tff : std_logic := '0';
362  signal rst_320_tff_buf : std_logic_vector(1 downto 0) := (Others => '0');
363  signal hub1_ila_error_bit, hub2_ila_error_bit : std_logic;
364  signal parity12, parity32 : std_logic;
365 
366 -- control reg signals
367 
368  signal xtal_ttc_sel, force_priv_rdout, crc_disable, ttc_enable, l1a_enable: std_logic;
369  signal rod_override, tob_aurora_en, raw_aurora_en, aurora_en: std_logic_vector(1 downto 0);
370  signal tob_ro_en, raw_ro_en, p_fpga_reset_125: std_logic_vector(3 downto 0);
371 
372 ---------------------------------------------------------------------------------------------------
373 -- ipbus buses signals
374  signal master_tx1_int, master_tx2_int, master_tx3_int, master_tx4_int : std_logic_vector(9 downto 0);
375  signal master_tx1_reg, master_tx2_reg, master_tx3_reg, master_tx4_reg : std_logic_vector(9 downto 0);
376  signal master_pause1_int, master_pause2_int, master_pause3_int, master_pause4_int : std_logic;
377  signal master_pause1_reg, master_pause2_reg, master_pause3_reg, master_pause4_reg : std_logic;
378  signal master_rx1_int, master_rx2_int, master_rx3_int, master_rx4_int : std_logic_vector(9 downto 0);
379  signal master_rx1_reg, master_rx2_reg, master_rx3_reg, master_rx4_reg : std_logic_vector(9 downto 0);
380  signal slaves_ipbus_up_int : std_logic_vector(3 downto 0);
381  signal dummy_tx1, dummy_tx2, dummy_tx3, dummy_tx4 : std_logic_vector(49 downto 5);
382  signal dummy_rx1, dummy_rx2, dummy_rx3, dummy_rx4 : std_logic_vector(54 downto 5);
383  signal i2c_sda_i, sda_o : std_logic;
384 ---------------------------------------------------------------------------------------------------
385  signal image_type : std_logic;
386 
387 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
388 -- Port signals
389 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
390 
391  signal ttc_L1A_p : std_logic_vector (3 downto 0);
392  signal ttc_L1A_n : std_logic_vector (3 downto 0);
393  signal ttc_BCR_p : std_logic_vector (3 downto 0);
394  signal ttc_BCR_n : std_logic_vector (3 downto 0);
395  signal ttc_ECR_p : std_logic_vector (3 downto 0);
396  signal ttc_ECR_n : std_logic_vector (3 downto 0);
397  signal ttc_pr_rdout_p : std_logic_vector (3 downto 0);
398  signal ttc_pr_rdout_n : std_logic_vector (3 downto 0);
399  signal ttc_info_F1 : std_logic_vector (37 downto 0);
400  signal ttc_info_F2 : std_logic_vector (37 downto 0);
401  signal ttc_info_F3 : std_logic_vector (37 downto 0);
402  signal ttc_info_F4 : std_logic_vector (37 downto 0);
403  signal ttc_parity_F1 : std_logic;
404  signal ttc_parity_F2 : std_logic;
405  signal ttc_parity_F3 : std_logic;
406  signal ttc_parity_F4 : std_logic;
407  signal aurora_hub1_txp : std_logic_vector (3 downto 0);
408  signal aurora_hub1_txn : std_logic_vector (3 downto 0);
409  signal aurora_hub2_txp : std_logic_vector (3 downto 0);
410  signal aurora_hub2_txn : std_logic_vector (3 downto 0);
411  signal cntl_RAW_rdy_F1_out : std_logic;
412  signal cntl_TOB_rdy_F1_out : std_logic;
413  signal cntl_RAW_rdy_F2_out : std_logic;
414  signal cntl_TOB_rdy_F2_out : std_logic;
415  signal cntl_RAW_rdy_F3_out : std_logic;
416  signal cntl_TOB_rdy_F3_out : std_logic;
417  signal cntl_RAW_rdy_F4_out : std_logic;
418  signal cntl_TOB_rdy_F4_out : std_logic;
419  signal txp_OUT : std_logic_vector(9 downto 0);
420  signal txn_OUT : std_logic_vector(9 downto 0);
421  signal sk14 : std_logic;
422  signal sk15 : std_logic;
423 
424  signal aurora_hub2_refclk1_p : std_logic;
425  signal aurora_hub2_refclk1_n : std_logic;
426  signal aurora_hub1_refclk1_p : std_logic;
427  signal aurora_hub1_refclk1_n : std_logic;
428  signal Q_CLK_GTREFCLK_PAD_N_IN : std_logic_vector(2 downto 0);
429  signal Q_CLK_GTREFCLK_PAD_P_IN : std_logic_vector(2 downto 0);
430  signal rxp_IN : std_logic_vector (9 downto 0);
431  signal rxn_IN : std_logic_vector (9 downto 0);
432  signal crc_error_i : std_logic_vector (1 downto 0);
433  signal reg_temp0, reg_temp1, ttc_enable_pulse: std_logic;
434 
435  signal aurora_1_gt0_txctrl_i,aurora_1_gt1_txctrl_i,aurora_1_gt2_txctrl_i,aurora_1_gt3_txctrl_i:std_logic_vector(23 downto 0);
436  signal aurora_2_gt0_txctrl_i,aurora_2_gt1_txctrl_i,aurora_2_gt2_txctrl_i,aurora_2_gt3_txctrl_i:std_logic_vector(23 downto 0);
437 
438 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
439 
440  attribute DONT_TOUCH : string;
441 -- attribute DONT_TOUCH of mac_clk : signal is "TRUE";
442  attribute DONT_TOUCH of ttc_BCR_i : signal is "TRUE";
443  attribute DONT_TOUCH of ttc_L1A_i : signal is "TRUE";
444  attribute DONT_TOUCH of ttc_ECR_i : signal is "TRUE";
445  attribute DONT_TOUCH of ttc_pr_rdout_i : signal is "TRUE";
446  attribute DONT_TOUCH of ttc_dummy_i : signal is "TRUE";
447  attribute DONT_TOUCH of ttc_ECRID_i : signal is "TRUE";
448  attribute DONT_TOUCH of ttc_L1ID_i : signal is "TRUE";
449  attribute DONT_TOUCH of ttc_parity_i : signal is "TRUE";
450 
451  attribute ASYNC_REG : string;
452  attribute ASYNC_REG of force_rx_error_buf : signal is "TRUE";
453  attribute ASYNC_REG of rst_320_tff_buf : signal is "TRUE";
454  attribute ASYNC_REG of hub1_combined_ttc_i : signal is "TRUE";
455  attribute ASYNC_REG of hub2_combined_ttc_i : signal is "TRUE";
456 
457 begin
458 
459 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
460 -- Port connection to signals
461 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
462  P_CONTROL_RECORD_TO_PORTS (
463  record_in => ctrl_in,
464  record_out => ctrl_out,
465  ttc_L1A_p => ttc_L1A_p,
466  ttc_L1A_n => ttc_L1A_n,
467  ttc_BCR_p => ttc_BCR_p,
468  ttc_BCR_n => ttc_BCR_n,
469  ttc_ECR_p => ttc_ECR_p,
470  ttc_ECR_n => ttc_ECR_n,
471  ttc_pr_rdout_p => ttc_pr_rdout_p,
472  ttc_pr_rdout_n => ttc_pr_rdout_n,
473  ttc_info_F1 => ttc_info_F1,
474  ttc_info_F2 => ttc_info_F2,
475  ttc_info_F3 => ttc_info_F3,
476  ttc_info_F4 => ttc_info_F4,
477  ttc_parity_F1 => ttc_parity_F1,
478  ttc_parity_F2 => ttc_parity_F2,
479  ttc_parity_F3 => ttc_parity_F3,
480  ttc_parity_F4 => ttc_parity_F4,
481  aurora_hub1_txp => aurora_hub1_txp,
482  aurora_hub1_txn => aurora_hub1_txn,
483  aurora_hub2_txp => aurora_hub2_txp,
484  aurora_hub2_txn => aurora_hub2_txn,
485  cntl_RAW_rdy_F1_out => cntl_RAW_rdy_F1_out,
486  cntl_TOB_rdy_F1_out => cntl_TOB_rdy_F1_out,
487  cntl_RAW_rdy_F2_out => cntl_RAW_rdy_F2_out,
488  cntl_TOB_rdy_F2_out => cntl_TOB_rdy_F2_out,
489  cntl_RAW_rdy_F3_out => cntl_RAW_rdy_F3_out,
490  cntl_TOB_rdy_F3_out => cntl_TOB_rdy_F3_out,
491  cntl_RAW_rdy_F4_out => cntl_RAW_rdy_F4_out,
492  cntl_TOB_rdy_F4_out => cntl_TOB_rdy_F4_out,
493  txp_OUT => txp_OUT,
494  txn_OUT => txn_OUT,
495  sk14 => sk14,
496  sk15 => sk15,
497  aurora_hub2_refclk1_p => aurora_hub2_refclk1_p,
498  aurora_hub2_refclk1_n => aurora_hub2_refclk1_n,
499  aurora_hub1_refclk1_p => aurora_hub1_refclk1_p,
500  aurora_hub1_refclk1_n => aurora_hub1_refclk1_n,
501  busy_raw => processor_busy_bus(7 downto 4),
502  busy_tob => processor_busy_bus(3 downto 0),
503  Q_CLK_GTREFCLK_PAD_N_IN => Q_CLK_GTREFCLK_PAD_N_IN,
504  Q_CLK_GTREFCLK_PAD_P_IN => Q_CLK_GTREFCLK_PAD_P_IN,
505  rxp_IN => rxp_IN,
506  rxn_IN => rxn_IN
507  );
508 
509  efex_number <= eFEX_mapping(to_integer(unsigned(hardware_addr(3 downto 0))));
510  sk14 <= '0';
511  sk15 <= '0';
512 
513 -------------------------------------------------------------
514 -- i2c bus settings
515 ------------------------------------------------------------
516  i2c_sda_i <= i2c_sda;
517  i2c_sda <= '0' when (sda_o = '0') else 'Z';
518  i2c_rst_0 <= '1'; -- This will be assigned active low reset signal
519 
520 --------------------------------------------------------------------
521  xtal_ttc_clk_sel <= xtal_ttc_sel;
522 
523 -- LEDs
524 -- f5_ipbus_access_led
525 -- f5_user_led_1
526 -- f5_ttc_clk_sel
527 -- fifos_full
528 -- l1a_stretch
529 
530 f5_ipbus_access_led_block : process(mac_clk) -- On for ~1/4 second if IPBus traffic or '1 Hz' blink, double blink if no IP address
531  variable counter_int: unsigned(25 downto 0) := (Others => '0');
532  constant all_ones: unsigned(25 downto 0) := (Others => '1');
533  variable led_lit, last_onehz, penultimate_onehz, no_ip_blink, reset_counter : std_logic := '0';
534  begin
535  if rising_edge(mac_clk) then
536  if rst_macclk = '1' then
537  reset_counter := '1';
538  led_lit := '0';
539  no_ip_blink := '0';
540  elsif mac_tx_last = '1' and mac_tx_valid = '1' and got_ip_address = '1' then -- EoP IPBus outbound
541  reset_counter := '1';
542  led_lit := '1';
543  no_ip_blink := '0';
544  elsif clk_locked = '1' and onehz = '1' and penultimate_onehz = '0' then -- '1 Hz blink'
545  reset_counter := '1';
546  led_lit := '1';
547  no_ip_blink := not got_ip_address;
548  elsif counter_int = all_ones then
549  reset_counter := '1';
550  led_lit := no_ip_blink; -- second blink if no IP address...
551  no_ip_blink := '0';
552  end if;
553  if reset_counter = '1' then
554  counter_int := (Others => '0');
555  else
556  if counter_int(25) = '1' then
557  led_lit := '0';
558  end if;
559  counter_int := counter_int + 1;
560  end if;
561  penultimate_onehz := last_onehz;
562  last_onehz := onehz;
563  reset_counter := '0';
564  f5_ipbus_access_led <= led_lit;
565  end if;
566  end process f5_ipbus_access_led_block;
567 
568  f5_user_led_1 <= '0' when GOLDEN else '1';
569  f5_ttc_clk_sel <= xtal_ttc_sel; -- Low indicates local crystal clock of 40.08MHz, high LHC TTC clock
570  fifos_full <= '0' when merged_busy_bus = x"00" else '1';
571 
572 l1a_stretch_block: process(clk40) -- On for ~1/2 second if L1A
573  variable counter_int: unsigned(22 downto 0) := (Others => '0');
574  constant all_ones: unsigned(22 downto 0) := (Others => '1');
575  variable led_lit, reset_counter: std_logic := '0';
576  begin
577  if rising_edge(clk40) then
578  if (reset = '1') then
579  reset_counter := '1';
580  led_lit := '0';
581  elsif counter_int = all_ones then
582  reset_counter := '1';
583  led_lit := '0';
584  elsif ttc_L1A = '1' and image_type = '1' then
585  reset_counter := '1';
586  led_lit := '1';
587  end if;
588  if reset_counter = '1' then
589  counter_int := (Others => '0');
590  else
591  counter_int := counter_int + 1;
592  end if;
593  reset_counter := '0';
594  l1a_stretch <= led_lit;
595  end if;
596  end process l1a_stretch_block;
597 
598  -- control fpga
599  -- moddule status assignement
600 
601  image_type <= '0' when GOLDEN else '1';
602 
603  Module_ID <= (31 => image_type, -- user (1) / golden image (0)
604  30 downto 28 => "000", -- FPGA flavour if 0 => control FPGA
605  27 downto 26 => "00", -- space for geographic address in process
606  25 downto 20 => serial_number,
607  19 downto 16 => hardware_addr(11 downto 8), -- shelf address
608  15 downto 12 => efex_number, -- true eFEX number!
609  11 downto 0 => X"efe" -- module ID
610  );
611 
612  status <= x"00000" & slaves_ipbus_up_int & fpga4_done & fpga3_done & fpga2_done & fpga1_done & locked & pll_lock_3 & '0' & pll_lock_1;
613 
614 -- Mapping of control signals from control_reg...
615 
616  xtal_ttc_sel <= control_reg(0); -- If low it selects local crystal clock of 40.08MHz. If high it selects LHC TTC clock
617  start <= control_reg(1); -- will start the synchronisation of incoming ttc information data with 40 MHz
618  POWERDN_B_CDCE <= not control_reg(2); --'1';
619  ftm_ttc_mode <= control_reg(3); -- Phase-I delay TTC info to processor FPGAs
620  phase2_ttc_mode <= control_reg(4); -- Phase-II delay TTC info to processor FPGAs (not implemented yet...)
621  crc_disable <= control_reg(5);
622  enable_pll_rst <= control_reg(6); -- This will generate active low pulse that will synchronous the PLLs (sync_b_cdce)
623  ttc_enable <= control_reg(7);
624  l1a_enable <= control_reg(8);
625  rod_override <= control_reg(10 downto 9);
626  tob_ro_en <= control_reg(15 downto 12);
627  raw_ro_en <= control_reg(19 downto 16);
628  tob_aurora_en <= control_reg(21 downto 20);
629  raw_aurora_en <= control_reg(23 downto 22);
630  aurora_en <= tob_aurora_en or raw_aurora_en;
631  phase2_ttc_delay_offset <= control_reg(29 downto 28); -- 0 = 8*32BC, 1 = 10*32BC, 2 = 12*32BC, 3 = 14*32BC
632  reconfig <= control_reg(30);
633 
634  master_link_down_int(0) <= not fpga1_done;
635  master_link_down_int(1) <= not fpga2_done;
636  master_link_down_int(2) <= not fpga3_done;
637  master_link_down_int(3) <= not fpga4_done;
638 
639 reset_and_reboot_block: process(ipb_clk)
640 -- Start timer on reconfig bit being set in control_reg
641 -- after 2 us (2^16 ticks) assert reset_phy
642 -- after 12 us assert trigger_reconfig
643  variable counter_int: unsigned(18 downto 0) := (Others => '0');
644  variable reset_phy_i, hold_counter: std_logic := '1';
645  variable trigger_reconfig_i: std_logic := '0';
646  begin
647  if rising_edge(ipb_clk) then
648  if (rst_ipb = '1') then
649  hold_counter := '1';
650  reset_phy_i := '0';
651  trigger_reconfig_i := '0';
652  elsif (reconfig = '1') then
653  hold_counter := '0';
654  end if;
655  if hold_counter = '1' then
656  counter_int := (Others => '0');
657  else
658  counter_int := counter_int + 1;
659  end if;
660  if (counter_int(16) = '1') then
661  reset_phy_i := '1';
662  end if;
663  if (counter_int(18 downto 17) = "11") then
664  trigger_reconfig_i := '1';
665  end if;
666  reset_phy <= reset_phy_i;
667  trigger_reconfig <= trigger_reconfig_i;
668  end if;
669  end process reset_and_reboot_block;
670 
671  phy_rstb <= not reset_phy;
672 
673 -- generate stretched mac_clk reset out of the original clocks_7s_extphy 'not locked' signal and rst_125
674 reset_macclk_block : process(mac_clk, clk_locked)
675  Variable reset_stretch: std_logic_vector(15 downto 0) := (Others => '1');
676  begin
677  if (clk_locked /= '1') then
678  rst_macclk <= '1';
679  reset_stretch := (Others => '1');
680  elsif rising_edge(mac_clk) then
681  rst_macclk <= reset_stretch(15);
682  if (rst_125 = '1') then
683  reset_stretch := (Others => '1');
684  else
685  reset_stretch := reset_stretch(14 downto 0) & "0";
686  end if;
687  end if;
688  end process reset_macclk_block;
689 
690 -- stretch link down a bit...
691 stretch_link_down_dly : for i in 0 to 3 generate
692  link_down_stretch : process(mac_clk)
693  Variable reset_stretch: std_logic_vector(15 downto 0) := (Others => '1');
694  begin
695  if rising_edge(mac_clk) then
696  master_link_down_dly(i) <= reset_stretch(15);
697  if (master_link_down_int(i) = '1') then
698  reset_stretch := (Others => '1');
699  else
700  reset_stretch := reset_stretch(14 downto 0) & "0";
701  end if;
702  end if;
703  end process link_down_stretch;
704  end generate stretch_link_down_dly;
705 
706 -- Disable incoming ethernet traffic if reconfig armed...
707  force_rx_error: process(mac_clk)
708  begin
709  if rising_edge(mac_clk) then
710  force_rx_error_buf <= force_rx_error_buf(0) & reconfig;
711  end if;
712  end process;
713 
714  my_rx_error <= mac_rx_error or force_rx_error_buf(1);
715 
716 -- Hold reset_125 high for Processor FPGAs and IPBus hub logic until Control FPGA has talked to the network
717 -- and/or that Processor has booted...
718 reset_125_block : process(mac_clk)
719  variable sent_first_packet : std_logic := '0';
720  begin
721  if rising_edge(mac_clk) then
722  if rst_macclk = '1' then
723  sent_first_packet := '0';
724  elsif mac_tx_last = '1' and mac_tx_valid = '1' and got_ip_address = '1' then
725  sent_first_packet := '1';
726  end if;
727  if sent_first_packet = '1' then
728  p_fpga_reset_125 <= control_reg(27 downto 24) or master_link_down_int or master_link_down_dly;
729  else
730  p_fpga_reset_125 <= (others => '1');
731  end if;
732  end if;
733  end process reset_125_block;
734 
735  reset_clk125 <= p_fpga_reset_125;
736 
737  global_ctrl_fabric : entity ipbus_lib.ipbus_fabric_sel
738  generic map(NSLV => N_SLAVES,
739  SEL_WIDTH => ipbus_sel_width)
740  port map(
741  ipb_in => ipb_out,
742  ipb_out => ipb_in,
743  sel => ipbus_sel_L1CaloEfex(ipb_out.ipb_addr),
744  ipb_to_slaves => ipbw,
745  ipb_from_slaves => ipbr
746  );
747 
748 
749 ---------------------------------------------------------------------------------
750  ----- common id registers slave
751  ---------------------------------------------------------------------------------------
752 
753  common_reg : entity infrastructure_lib.common_id_registers
754  port map (
755  ipb_clk => ipb_clk,
756  ipb_rst => rst_ipb,
757  ipb_in => ipbw(N_SLV_COMMON_ID_VERSION),
758  ipb_out => ipbr(N_SLV_COMMON_ID_VERSION),
759  Module_ID => Module_ID,
760  xml_version => XML_VER,
761  xml_Gitsha => XML_SHA,
762  fw_version => GLOBAL_VER,
763  fw_Gitsha => GLOBAL_SHA,
764  build_date => GLOBAL_DATE,
765  build_time => GLOBAL_TIME
766 
767  );
768 
769 
770  U_0 : entity infrastructure_lib.top_udp_config_FPGA
771  port map (
772  ipb_clk => ipb_clk,
773  ipb_in => ipb_in, --ipb_master_in,
774  ipb_out => ipb_out, --ipb_master_out,
775  hardware_addr => hardware_addr,
776  serial_number => serial_number,
777  mac_clk => mac_clk,
778  mac_rx_data => mac_rx_data,
779  mac_rx_error => my_rx_error,
780  mac_rx_last => mac_rx_last,
781  mac_rx_valid => mac_rx_valid,
782  mac_tx_ready => mac_tx_ready,
783  master_tx_data1 => master_tx_data1_int,
784  master_tx_data2 => master_tx_data2_int,
785  master_tx_data3 => master_tx_data3_int,
786  master_tx_data4 => master_tx_data4_int,
787  master_tx_err1 => master_tx_err1,
788  master_tx_err2 => master_tx_err2,
789  master_tx_err3 => master_tx_err3,
790  master_tx_err4 => master_tx_err4,
791  rst_ipb => rst_ipb_ctrl,
792  rst_macclk => rst_macclk,
793  p_fpga_reset_125 => p_fpga_reset_125,
794  mac_tx_data => mac_tx_data,
795  mac_tx_error => mac_tx_error,
796  mac_tx_last => mac_tx_last,
797  mac_tx_valid => mac_tx_valid,
798  master_rx_data1 => master_rx_data1_int,
799  master_rx_data2 => master_rx_data2_int,
800  master_rx_data3 => master_rx_data3_int,
801  master_rx_data4 => master_rx_data4_int,
802  master_tx_pause1 => master_pause1_int, --to iodelay
803  master_tx_pause2 => master_pause2_int, --to iodelay
804  master_tx_pause3 => master_pause3_int, --to iodelay
805  master_tx_pause4 => master_pause4_int, --to iodelay
806  master_link_down1 => master_link_down_int(0),
807  master_link_down2 => master_link_down_int(1),
808  master_link_down3 => master_link_down_int(2),
809  master_link_down4 => master_link_down_int(3),
810  got_ip_address => got_ip_address,
811  slaves_ipbus_up => slaves_ipbus_up_int
812  );
813 
814 
815  ------- -- Interconnection between control FPGA and Process FPGA1------------------
816 
817  U_1 : entity infrastructure_lib.interconnect
818  port map (
819  mac_clk => mac_clk,
820  master_rx_data => master_tx1_int, -- coming from FPGA1
821  rst_macclk => rst_macclk,
822  tx_data => master_rx_data1_int,
823  master_rx_err => master_tx_err1, -- is set high if data has parity error
824  process_tx_data => master_rx1_int, -- goes to iodelay and then to FPGA1
825  rx_data => master_tx_data1_int -- goes to top_udp_config block
826  );
827 
828  ------- -- Interconnection between control FPGA and Process FPGA2------------------
829  U_2 : entity infrastructure_lib.interconnect
830  port map (
831  mac_clk => mac_clk,
832  master_rx_data => master_tx2_int, -- coming from FPGA2
833  rst_macclk => rst_macclk,
834  tx_data => master_rx_data2_int,
835  master_rx_err => master_tx_err2, -- is set high if data has parity error
836  process_tx_data => master_rx2_int, -- goes to iodelay and then to FPGA2
837  rx_data => master_tx_data2_int -- goes to top_udp_config block
838  );
839 
840 ------- -- Interconnection between control FPGA and Process FPGA3------------------
841 
842  U_3 : entity infrastructure_lib.interconnect
843  port map (
844  mac_clk => mac_clk,
845  master_rx_data => master_tx3_int, -- coming from FPGA3
846  rst_macclk => rst_macclk,
847  tx_data => master_rx_data3_int,
848  master_rx_err => master_tx_err3, -- is set high if data has parity error
849  process_tx_data => master_rx3_int, -- goes to iodelay and then to FPGA3
850  rx_data => master_tx_data3_int -- goes to top_udp_config block
851  );
852  ------- -- Interconnection between control FPGA and Process FPGA4------------------
853 
854  U_4 : entity infrastructure_lib.interconnect
855  port map (
856  mac_clk => mac_clk,
857  master_rx_data => master_tx4_int, -- coming from FPGA4
858  rst_macclk => rst_macclk,
859  tx_data => master_rx_data4_int,
860  master_rx_err => master_tx_err4, -- is set high if data has parity error
861  process_tx_data => master_rx4_int, -- goes to iodelay and then to FPGA4
862  rx_data => master_tx_data4_int -- goes to top_udp_config block
863  );
864 
865  -- DCM clock generation for internal bus, ethernet
866  clocks : entity infrastructure_lib.clocks_7s_extphy
867  port map(
868  sysclk_p => gt_clk125_p,
869  sysclk_n => gt_clk125_n,
870  clko_125 => mac_clk,
871  clko_200 => clk200,
872  clko_ipb => ipb_clk,
873  locked => clk_locked,
874  rsto_125 => rst_125,
875  rsto_ipb => rst_ipb,
876  rsto_ipb_ctrl => rst_ipb_ctrl,
877  onehz => onehz
878  );
879 
880 -- --- Ethernet MAC core and PHY interface
881  eth : entity infrastructure_lib.eth_7s_gmii
882  port map(
883  clk125 => mac_clk,
884  clk200 => clk200,
885  rst => rst_macclk,
886  gmii_gtx_clk => gmii_gtx_clk,
887  gmii_txd => gmii_txd,
888  gmii_tx_en => gmii_tx_en,
889  gmii_tx_er => gmii_tx_er,
890  gmii_rx_clk => gmii_rx_clk,
891  gmii_rxd => gmii_rxd,
892  gmii_rx_dv => gmii_rx_dv,
893  gmii_rx_er => gmii_rx_er,
894  tx_data => mac_tx_data,
895  tx_valid => mac_tx_valid,
896  tx_last => mac_tx_last,
897  tx_error => mac_tx_error,
898  tx_ready => mac_tx_ready,
899  rx_data => mac_rx_data,
900  rx_valid => mac_rx_valid,
901  rx_last => mac_rx_last,
902  rx_error => mac_rx_error
903 
904  );
905 
906 
907 -----------------------------------------------------------------------------------------------------------------------------------------------------------------------
908  -- ipbus slaves live in the entity below, and can expose top-level ports
909 -- The ipbus fabric is instantiated within.
910 --------------------------------------------------------------------------------------------------------
911 
912  infrastructure_control : entity infrastructure_lib.infrastructure_slaves_cntrl
913  port map(
914  ipb_clk => ipb_clk,
915  ipb_rst => rst_ipb,
916  ipb_in => ipbw(N_SLV_CNTRL_INFRA),
917  ipb_out => ipbr(N_SLV_CNTRL_INFRA),
918  status => status,
919  control_reg => control_reg,
920  reconfig_reg => reconfig_reg,
921  VAUXP => VAUXP,
922  VAUXN => VAUXN,
923  Vp => Vp,
924  Vn => Vn,
925 
926  scl => i2c_scl,
927  sda_i => i2c_sda_i,
928  sda_o => sda_o,
929 
930  pll_clko => pll_clko,
931  pll_le => pll_en,
932  pll_miso => pll_miso,
933  pll_mosi => pll_mosi,
934  pll_select => select_pll,
935  flash_miso => flash_miso,
936  flash_le => flash_csn,
937  flash_clko => flash_clk,
938  flash_mosi => flash_mosi
939 
940  );
941 
942 
943 ----------------------------------------------------
944 --- pll select and flash
945 ------------------------------------------------------
946 
947  pll_sel : entity infrastructure_lib.pll_selector
948  port map
949  (
950  sel => select_pll(1 downto 0),
951  pll_en_1 => pll_le_1,
952  pll_en_3 => pll_le_3,
953  pll_en => pll_en
954 
955  );
956 
957 
958  cclk_o : entity infrastructure_lib.startup
959  port map(
960  flash_cclk => flash_clk
961  );
962 
963 ------------------------------------------------------------
964 ---- generate config pulse
965 --------------------------------------------------------------
966  configure : entity infrastructure_lib.reconfig
967  generic map (MAX_COUNT => 1)
968  port map(
969  WBSTAR => reconfig_reg,
970  sysclk => ipb_clk, --icap_clk,
971  trigger => trigger_reconfig
972  );
973 -------------------------------------------------------
974 --- clock generation of 40M,160M and 280M from the TTC
975 ------------------------------------------------------
976  ttc_clk : clk_ttc
977  port map (
978  -- Clock out ports
979  clk40 => clk40,
980  clk320 => clk320,
981  clk160 => clk160,
982  -- Status and control signals
983  locked => locked,
984  -- Clock in ports
985  clk_in1_p => clk_40_p,
986  clk_in1_n => clk_40_n
987  );
988 
989 -- generate stretched 40 MHz resets out of the original asynchronous 'not locked' signal and the ttc_enable_pulse
990  reset_clk40 : process(clk40, locked)
991  Variable reset_stretch, ttc_stretch: std_logic_vector(15 downto 0) := (Others => '1');
992  begin
993  if (locked /= '1') then
994  reset <= '1';
995  ttc_fifo_reset <= '1';
996  reset_stretch := (Others => '1');
997  ttc_stretch := (Others => '1');
998  elsif rising_edge(clk40) then
999  reset <= reset_stretch(15);
1000  ttc_fifo_reset <= ttc_stretch(15);
1001  if (ttc_enable_pulse = '1') then
1002  ttc_stretch := (Others => '1');
1003  else
1004  ttc_stretch := ttc_stretch(14 downto 0) & "0";
1005  end if;
1006  reset_stretch := reset_stretch(14 downto 0) & "0";
1007  end if;
1008  end process reset_clk40;
1009 
1010  reset_pll : entity infrastructure_lib.nreset_pll
1011  port map(
1012  clk40 => clk40,
1013  enable_pll_rst => enable_pll_rst,
1014  rst_ipb => rst_ipb,
1015  SYNC_B_CDCE => SYNC_B_CDCE
1016 
1017  );
1018 
1019 -- Register IPBus interFPGA signals
1020  IPBusReg : process(mac_clk)
1021  begin
1022  if rising_edge(mac_clk) then
1023  master_tx1_int <= master_tx1_reg;
1024  master_tx2_int <= master_tx2_reg;
1025  master_tx3_int <= master_tx3_reg;
1026  master_tx4_int <= master_tx4_reg;
1027 
1028  master_rx1_reg <= master_rx1_int;
1029  master_pause1_reg <= master_pause1_int;
1030  master_rx2_reg <= master_rx2_int;
1031  master_pause2_reg <= master_pause2_int;
1032  master_rx3_reg <= master_rx3_int;
1033  master_pause3_reg <= master_pause3_int;
1034  master_rx4_reg <= master_rx4_int;
1035  master_pause4_reg <= master_pause4_int;
1036  end if;
1037  end process IPBusReg;
1038 
1039 -- Inter-FPGA IO on falling edge...
1040  IPBusIO : process(mac_clk)
1041  begin
1042  if falling_edge(mac_clk) then
1043  master_tx1_reg <= master_tx_data1;
1044  master_tx2_reg <= master_tx_data2;
1045  master_tx3_reg <= master_tx_data3;
1046  master_tx4_reg <= master_tx_data4;
1047 
1048  master_rx_data1 <= master_rx1_reg;
1049  master_tx_pause1 <= master_pause1_reg;
1050  master_rx_data2 <= master_rx2_reg;
1051  master_tx_pause2 <= master_pause2_reg;
1052  master_rx_data3 <= master_rx3_reg;
1053  master_tx_pause3 <= master_pause3_reg;
1054  master_rx_data4 <= master_rx4_reg;
1055  master_tx_pause4 <= master_pause4_reg;
1056  end if;
1057  end process IPBusIO;
1058 
1059 
1060  GOLDEN_IF : if not GOLDEN generate
1061 
1062 ----------------------------------------------------------
1063 --- control fpga mgts.
1064 ----------------------------------------------------------
1065  RXN_IN_i <= "00" & RXN_IN;
1066  RXP_IN_i <= "00" & RXP_IN;
1067  TXN_OUT <= TXN_OUT_i(9 downto 0);
1068  TXP_OUT <= TXP_OUT_i(9 downto 0);
1069 
1070  MGT_TX_RX : entity work.top_mgt_cfpga
1071 
1072  generic map (NPROCESSORFPGA => N_PROCESSORFPGA)
1073  port map (
1074  start => start,
1075  clk40 => clk40,
1076  clk160 => clk160,
1077  rx_clk160 => rx_clk160,
1078  rx_clk280 => rx_clk280,
1079  Q_CLK_GTREFCLK_PAD_N_IN => Q_CLK_GTREFCLK_PAD_N_IN, -- (1 downto 0),
1080  Q_CLK_GTREFCLK_PAD_P_IN => Q_CLK_GTREFCLK_PAD_P_IN, -- (1 downto 0),
1081  RXN_IN => RXN_IN_i,
1082  RXP_IN => RXP_IN_i,
1083  TXN_OUT => TXN_OUT_i,
1084  TXP_OUT => TXP_OUT_i,
1085  rx_resetdone => rx_resetdone,
1086  rx_fsm_resetdone => rx_fsm_resetdone,
1087  rx_byteisaligned => rx_byteisaligned,
1088  tx_resetdone => tx_resetdone,
1089  tx_fsm_resetdone => tx_fsm_resetdone,
1090  tx_bufstatus => tx_bufstatus,
1091  rx_realign => rx_realign,
1092  rx_disperr => rx_disperr,
1093  encode_error => encode_error,
1094  mgt_commadret => mgt_commadret,
1095  loopback => loopback,
1096  mgt_SOFT_RESET_TX_IN => softreset_tx,
1097  mgt_SOFT_RESET_RX_IN => softreset_rx,
1098  mgt_QPLLLOCK_OUT => qpll_lock,
1099  mgt_QPLLREFCLKLOST_OUT => qpll_refclklost,
1100 -- data from MGT
1101  data_from_mgt_bus => data_from_mgt_bus, -- first TOB then Input Data for each FPGA in turn
1102  char_is_k_bus => char_is_k_bus, -- first TOB then Input Data for each FPGA in turn
1103  error_from_mgt_bus => error_from_mgt_bus, -- first TOB then Input Data for each FPGA in turn
1104  hub1_rx_data => hub1_rx_data,
1105  hub2_rx_data => hub2_rx_data
1106  );
1107 
1108 -- mgt_xoff_bus in Processor Number order, (3 downto 0) TOBs (7 downto 4) Input Data
1109 
1110  cntl_TOB_rdy_F1_out <= not mgt_xoff_bus(0);
1111  cntl_TOB_rdy_F2_out <= not mgt_xoff_bus(3);
1112  cntl_TOB_rdy_F3_out <= not mgt_xoff_bus(1);
1113  cntl_TOB_rdy_F4_out <= not mgt_xoff_bus(2);
1114  cntl_RAW_rdy_F1_out <= not mgt_xoff_bus(4);
1115  cntl_RAW_rdy_F2_out <= not mgt_xoff_bus(7);
1116  cntl_RAW_rdy_F3_out <= not mgt_xoff_bus(5);
1117  cntl_RAW_rdy_F4_out <= not mgt_xoff_bus(6);
1118 
1119 --------------------------------------------------------------------------
1120 -------Incoming backplane data
1121 --------------------------------------------------------------------------
1122 
1123 ttcenable_pulse: process(clk40)
1124  begin
1125  if clk40' event and clk40 = '1' then
1126  reg_temp0 <= ttc_enable;
1127  reg_temp1 <= reg_temp0 ;
1128  ttc_enable_pulse <= reg_temp0 and not reg_temp1 ; -- this will create ttc_enable pulse for reseting the crc state machine, also used to reset TTC FIFOs
1129  end if;
1130  end process;
1131 
1132 --- Hub 1 synchronisation block
1133  synch_ttc_combined : entity infrastructure_lib.top_cntrl_synch
1134  port map (
1135  rx_clk160 => rx_clk160(0), --8 -- rx clock of the mgt114
1136  TTC_clk => clk40, -- ttc clock of 40 MHz
1137  reset => reset,
1138  enable_mgt => mgt_enable(0), -- enaable of the incoming rx data
1139  MGT_Commadet => mgt_commadret(0), --8 -- comma detected for incoming data
1140  reg_sel => bc_reg_sel(3 downto 0), -- setting BC mux --
1141  mux_sel => mux_sel(3 downto 0), -- setting the first stage mux
1142  delay_num => delay_cntr_0, -- delay count of first stage
1143  start => start, -- start pulse for the calibration to start
1144  rx_resetdone => rx_resetdone(8), --rx_resetdone(2),
1145  reg128_latch => reg128_latch,
1146  data_out => hub1_combined_ttc_rxclk, -- ttc_information synch goes to process fpgasdata_out_reg128, ---data_out_reg128,
1147  data_in => hub1_rx_data, -- in coming ttc information data
1148  crc_error_in => crc_error_i(0)
1149  );
1150 
1151  crc_checker_hub1 : entity infrastructure_lib.cntrl_crc_checker
1152  port map (
1153  clk => rx_clk160(0),
1154  reset => ttc_enable_pulse,
1155  mgt_enable => mgt_enable(0),
1156  mgt_commdet => mgt_commadret(0),
1157  rxdata => hub1_rx_data,
1158  crc_error => crc_error_i(0)
1159  );
1160 
1161  hub1_ila_error_block: process(rx_clk160(0))
1162  begin
1163  if rising_edge(rx_clk160(0)) then
1164 -- Quad 114 error bits
1165 -- rx_realign => rx_realign(11 downto 8) ,
1166 -- rx_disperr => rx_disperr(47 downto 32),
1167 -- encode_error => encode_error(47 downto 32) ,
1168  if (rx_realign(8) = '0') and (rx_disperr(35 downto 32) = x"0") and (encode_error(35 downto 32) = x"0") then
1169  hub1_ila_error_bit <= '0';
1170  else
1171  hub1_ila_error_bit <= '1';
1172  end if;
1173  end if;
1174  end process hub1_ila_error_block;
1175 
1176  crc_ila_hub1 : ila_1
1177  port map (
1178  clk => rx_clk160(0),
1179  probe0(31 downto 0) => hub1_rx_data,
1180  probe0(32) => mgt_commadret(0),
1181  probe0(33) => hub1_ila_error_bit,
1182  probe0(34) => crc_error_i(0)
1183  );
1184 
1185  process(clk40)
1186  begin
1187  if clk40' event and clk40 = '1' then
1188  hub1_combined_ttc_i <= hub1_combined_ttc_rxclk;
1189  end if;
1190  end process;
1191 
1192  process(clk40)
1193  begin
1194  if clk40' event and clk40 = '1' then
1195  if (ttc_enable = '1') then -- only listen once TTC has been declared valid
1196  if ((hub1_combined_ttc_i(128) = '0') or (crc_disable = '1')) and (hub1_combined_ttc_i(7 downto 0) = x"BC") then -- and CRC and K char is valid...
1197  hub1_combined_ttc(128 downto 105) <= hub1_combined_ttc_i(128 downto 105);
1198  hub1_combined_ttc(104) <= (hub1_combined_ttc_i(104) and aurora_en(0)) or rod_override(0); -- ROD link enable if Aurora link enabled or ROD override set
1199  hub1_combined_ttc(103 downto 101) <= hub1_combined_ttc_i(103 downto 101);
1200  hub1_combined_ttc(100) <= (hub1_combined_ttc_i(100) and aurora_en(0)) or rod_override(0); -- ROD link up if Aurora link enabled or ROD override set
1201  hub1_combined_ttc(99 downto 97) <= hub1_combined_ttc_i(99 downto 97);
1202  hub1_combined_ttc(96) <= hub1_combined_ttc_i(96) and aurora_en(0) and not rod_override(0); -- ROD reset only if Aurora link enabled and ROD override disabled
1203  hub1_combined_ttc(95 downto 17) <= hub1_combined_ttc_i(95 downto 17);
1204  hub1_combined_ttc(16) <= hub1_combined_ttc_i(16) and l1a_enable; -- and only assert L1A when enabled
1205  hub1_combined_ttc(15 downto 0) <= hub1_combined_ttc_i(15 downto 0);
1206  hub1_combined_ttc_valid <= '1';
1207  else
1208  hub1_combined_ttc(128 downto 105) <= (Others => '0');
1209  hub1_combined_ttc(104) <= hub1_combined_ttc(104) or rod_override(0); -- latch ROD link status or ROD override...
1210  hub1_combined_ttc(103 downto 101) <= (Others => '0');
1211  hub1_combined_ttc(100) <= hub1_combined_ttc(100) or rod_override(0); -- latch ROD link status or ROD override...
1212  hub1_combined_ttc(99 downto 97) <= (Others => '0');
1213  hub1_combined_ttc(96) <= hub1_combined_ttc(96) and not rod_override(0); -- latch ROD link status or ROD override...
1214  hub1_combined_ttc(95 downto 0) <= (Others => '0');
1215  hub1_combined_ttc_valid <= '0';
1216  end if;
1217  else
1218  hub1_combined_ttc <= (Others => '0');
1219  hub1_combined_ttc_valid <= '0';
1220  end if;
1221  hub1_combined_ttc_ila <= hub1_combined_ttc_i;
1222  end if;
1223  end process;
1224 
1225 ---- Hub 2 synchronisation block
1226  synch_hub2_combined_ttc : entity infrastructure_lib.top_cntrl_synch
1227  port map (
1228  rx_clk160 => rx_clk160(1), --9 -- rx clock of the mgt114
1229  TTC_clk => clk40, -- ttc clock of 40 MHz
1230  reset => reset,
1231  enable_mgt => mgt_enable(1), -- enaable of the incoming rx data
1232  MGT_Commadet => mgt_commadret(1), --9 comma detected for incoming data
1233  reg_sel => bc_reg_sel(7 downto 4), -- setting BC mux --
1234  mux_sel => mux_sel(7 downto 4), -- setting the first stage mux
1235  delay_num => delay_cntr_1, -- delay count of first stage
1236  start => start, -- start pulse for the calibration to start
1237  rx_resetdone => rx_resetdone(9), --rx_resetdone(3),
1238  reg128_latch => hub2_combined_ttc_latch,
1239  data_out => hub2_combined_ttc_rxclk, -- ttc_information synch goes to process fpgasdata_out_reg128, ---data_out_reg128,
1240  data_in => hub2_rx_data, --rod_busy -- in coming ttc information data
1241  crc_error_in => crc_error_i(1)
1242  );
1243 
1244  crc_checker_hub2 : entity infrastructure_lib.cntrl_crc_checker
1245  port map (
1246  clk => rx_clk160(1),
1247  reset => ttc_enable_pulse,
1248  mgt_enable => mgt_enable(1),
1249  mgt_commdet => mgt_commadret(1),
1250  rxdata => hub2_rx_data,
1251  crc_error => crc_error_i(1)
1252  );
1253 
1254 -- hub2_ila_error_block: process(rx_clk160(1))
1255 -- begin
1256 -- if rising_edge(rx_clk160(1)) then
1257 -- -- Quad 114 error bits
1258 -- -- rx_realign => rx_realign(11 downto 8) ,
1259 -- -- rx_disperr => rx_disperr(47 downto 32),
1260 -- -- encode_error => encode_error(47 downto 32) ,
1261 -- if (rx_realign(9) = '0') and (rx_disperr(39 downto 36) = x"0") and (encode_error(39 downto 36) = x"0") then
1262 -- hub2_ila_error_bit <= '0';
1263 -- else
1264 -- hub2_ila_error_bit <= '1';
1265 -- end if;
1266 -- end if;
1267 -- end process hub2_ila_error_block;
1268 --
1269 -- crc_ila_hub2 : ila_1
1270 -- port map (
1271 -- clk => rx_clk160(1),
1272 -- probe0(31 downto 0) => hub2_rx_data,
1273 -- probe0(32) => mgt_commadret(1),
1274 -- probe0(33) => hub2_ila_error_bit,
1275 -- probe0(34) => crc_error_i(1)
1276 -- );
1277 
1278  process(clk40)
1279  begin
1280  if clk40' event and clk40 = '1' then
1281  hub2_combined_ttc_i <= hub2_combined_ttc_rxclk;
1282  end if;
1283  end process;
1284 
1285  process(clk40)
1286  begin
1287  if clk40' event and clk40 = '1' then
1288  if (ttc_enable = '1') and (aurora_en(1) = '1') then -- only listen once TTC has been declared valid and this Aurora link is enabled
1289  if ((hub2_combined_ttc_i(128) = '0') or (crc_disable = '1')) and (hub2_combined_ttc_i(7 downto 0) = x"BC") then -- and CRC and K char is valid...
1290  hub2_combined_ttc(128 downto 105) <= hub2_combined_ttc_i(128 downto 105);
1291  hub2_combined_ttc(104) <= hub2_combined_ttc_i(104) or rod_override(1); -- force link enable if ROD override set
1292  hub2_combined_ttc(103 downto 101) <= hub2_combined_ttc_i(103 downto 101);
1293  hub2_combined_ttc(100) <= hub2_combined_ttc_i(100) or rod_override(1); -- force link up if ROD override set
1294  hub2_combined_ttc(99 downto 97) <= hub2_combined_ttc_i(99 downto 97);
1295  hub2_combined_ttc(96) <= hub2_combined_ttc_i(96) and not rod_override(1); -- force reset off if ROD override set
1296  hub2_combined_ttc(95 downto 0) <= hub2_combined_ttc_i(95 downto 0);
1297  hub2_combined_ttc_valid <= '1';
1298  else
1299  hub2_combined_ttc(128 downto 105) <= (Others => '0');
1300  hub2_combined_ttc(104) <= hub2_combined_ttc(104) or rod_override(1); -- latch ROD link status or ROD override...
1301  hub2_combined_ttc(103 downto 101) <= (Others => '0');
1302  hub2_combined_ttc(100) <= hub2_combined_ttc(100) or rod_override(1); -- latch ROD link status or ROD override...
1303  hub2_combined_ttc(99 downto 97) <= (Others => '0');
1304  hub2_combined_ttc(96) <= hub2_combined_ttc(96) and not rod_override(1); -- latch ROD link status or ROD override...
1305  hub2_combined_ttc(95 downto 0) <= (Others => '0');
1306  hub2_combined_ttc_valid <= '0';
1307  end if;
1308  else
1309  hub2_combined_ttc <= (Others => '0');
1310  hub2_combined_ttc_valid <= '0';
1311  end if;
1312  hub2_combined_ttc_ila <= hub2_combined_ttc_i;
1313  end if;
1314  end process;
1315 
1316  bcn_counter : process(clk40)
1317  variable bcn_count : unsigned (11 downto 0) := (others => '0');
1318  begin
1319 -- switch this on hub1_combined_ttc_i so that bcn_cntr is in time with hub1_combined_ttc a tick later...
1320  if clk40' event and clk40 = '1' then
1321  if ((hub1_combined_ttc_i(17) = '1') and (hub1_combined_ttc_i(128) = '0') and (hub1_combined_ttc_i(7 downto 0) = x"BC")) or (bcn_count = 3563) then -- wrap around to zero at end of orbit
1322  bcn_count := (others => '0');
1323  else
1324  bcn_count := bcn_count + 1;
1325  end if;
1326  bcn_cntr <= std_logic_vector(bcn_count);
1327  end if;
1328  end process bcn_counter;
1329 
1330  Aurora_link_control : process(clk40)
1331  begin
1332  if rising_edge(clk40) then
1333  if (hub1_combined_ttc(100) = '1') and (hub1_combined_ttc(104) = '1') then -- ROD1 link up and enabled
1334  tob_xoff_bus(0) <= hub1_combined_ttc(8);
1335  raw_xoff_bus(0) <= hub1_combined_ttc(9);
1336  else
1337  tob_xoff_bus(0) <= '1';
1338  raw_xoff_bus(0) <= '1';
1339  end if;
1340  if (hub2_combined_ttc(100) = '1') and (hub2_combined_ttc(104) = '1') then -- ROD2 link up and enabled
1341  tob_xoff_bus(1) <= hub2_combined_ttc(8);
1342  raw_xoff_bus(1) <= hub2_combined_ttc(9);
1343  else
1344  tob_xoff_bus(1) <= '1';
1345  raw_xoff_bus(1) <= '1';
1346  end if;
1347  link_reset_hub1 <= hub1_combined_ttc(96);
1348  link_reset_hub2 <= hub2_combined_ttc(96);
1349  end if;
1350  end process Aurora_link_control;
1351 
1352  ttc_din <= "000000" & hub1_combined_ttc(63 downto 32) & bcn_cntr; -- Phase-I TTC ECRID, L1ID and BCN
1353 
1354  priv_rdout_block: process(clk40)
1355  variable l1id_match: unsigned(23 downto 0) := (Others => '0');
1356  variable pulse_readout: std_logic := '0';
1357  begin
1358  if rising_edge(clk40) then
1359  if (hub1_combined_ttc(18) = '1') then -- ttc_ECR, reset match to 0
1360  l1id_match := (Others => '0');
1361  elsif (hub1_combined_ttc(16) = '1') then -- ttc_L1A
1362  if (unsigned(hub1_combined_ttc(55 downto 32)) >= l1id_match) then -- ttc_L1ID
1363  l1id_match := l1id_match + unsigned(input_data_readout_control(31 downto 8)); -- increment match by prescale_factor
1364  end if;
1365  pulse_readout := '0';
1366  end if;
1367  priv_rdout_l1id <= std_logic_vector(l1id_match);
1368  priv_rdout_reg_1 <= input_data_readout_control(0); -- pulse_request
1369  priv_rdout_reg_2 <= priv_rdout_reg_1;
1370  if (priv_rdout_reg_1 = '1' and priv_rdout_reg_2 = '0') then -- latch pulse request until next L1A
1371  pulse_readout := '1';
1372  end if;
1373  if (pulse_readout = '1') or (input_data_readout_control(2) = '1') then -- pulse or force request
1374  force_priv_rdout <= '1';
1375  else
1376  force_priv_rdout <= '0';
1377  end if;
1378  end if;
1379  end process priv_rdout_block;
1380 
1381  ttc_block: process(clk40)
1382  begin
1383  if rising_edge(clk40) then
1384  ttc_L1A <= hub1_combined_ttc(16); -- L1 accept to indicate when an event has been accepted
1385  ttc_BCR <= hub1_combined_ttc(17); -- bunch counter reset. used to reset local bc counters
1386  ttc_ECR <= hub1_combined_ttc(18); -- event counter reset
1387  if hub1_combined_ttc(16) = '1' then -- L1A
1388  ttc_ECRID <= hub1_combined_ttc(63 downto 56); -- Incoming ECRID
1389  ttc_L1ID <= hub1_combined_ttc(55 downto 32); -- Incoming L1ID
1390  if (input_data_readout_control(1) = '1') and (hub1_combined_ttc(55 downto 32) = priv_rdout_l1id) then -- prescaled readout
1391  ttc_pr_rdout <= '1';
1392  else
1393  ttc_pr_rdout <= force_priv_rdout; -- pulse or force request
1394  end if;
1395  else -- encode BCN in L1ID
1396  ttc_ECRID <= (Others => '0');
1397  ttc_L1ID <= x"000" & bcn_cntr;
1398  ttc_pr_rdout <= '0';
1399  end if;
1400  end if;
1401  end process ttc_block;
1402 
1403  d_i <= ttc_L1ID & ttc_ECRID & ttc_pr_rdout & ttc_ECR & ttc_BCR & ttc_L1A;
1404 
1405  combined_ttc_ila : ila_0
1406  port map (
1407  clk => clk40,
1408  probe0(11 downto 0) => hub1_combined_ttc_ila(11 downto 0), -- K28.5, TOB XOFF, Input Data XOFF, System_Reset Hub1
1409  probe0(15 downto 12) => hub1_combined_ttc_ila(19 downto 16), -- L1A, BCR, ECR, Priv Readout (Hub 1)
1410  probe0(47 downto 16) => hub1_combined_ttc_ila(63 downto 32), -- L1ID (Hub 1)
1411  probe0(48) => hub1_combined_ttc_ila(96), -- link_reset Hub1
1412  probe0(49) => hub1_combined_ttc_ila(100), -- link_up Hub1
1413  probe0(50) => hub1_combined_ttc_ila(104), -- link_enable Hub1
1414  probe0(51) => hub1_combined_ttc_ila(128), -- CRC result
1415  probe0(63 downto 52) => hub2_combined_ttc_ila(11 downto 0), -- K28.5, TOB XOFF, Input Data XOFF, System_Reset Hub2
1416  probe0(65 downto 64) => hub2_combined_ttc_ila(17 downto 16), -- Hub2 delayed L1A and BCR
1417  probe0(66) => hub2_combined_ttc_ila(96), -- link_reset Hub2
1418  probe0(67) => hub2_combined_ttc_ila(100), -- link_up Hub2
1419  probe0(68) => hub2_combined_ttc_ila(104), -- link_enable Hub2
1420  probe0(69) => hub2_combined_ttc_ila(128) -- CRC result
1421  );
1422 
1423  ftm_ttc_mode_sel : process(clk40)
1424  begin
1425  if clk40' event and clk40 = '1' then
1426  if ftm_ttc_mode = '1' then
1427  q_i <= g_i;
1428  else
1429  q_i <= d_i;
1430  end if;
1431  end if;
1432  end process;
1433 
1434  shift_mux36_d : for i in 0 to 35 generate
1435  SRLC32E_inst_12 : SRLC32E
1436  generic map (
1437  INIT => X"00000000")
1438  port map (
1439  Q => Open,
1440  Q31 => e_i(i), -- SRL cascaded data output
1441  A => (Others => '1'), -- Select input
1442  CE => '1', -- Clock enable input
1443  CLK => CLK40, -- Clock input
1444  D => d_i(i) -- SRL data input
1445  );
1446  end generate shift_mux36_d;
1447 
1448  shift_mux36_e : for i in 0 to 35 generate
1449  SRLC32E_inst_12 : SRLC32E
1450  generic map (
1451  INIT => X"00000000")
1452  port map (
1453  Q => Open,
1454  Q31 => f_i(i), -- SRL cascaded data output
1455  A => (Others => '1'), -- Select input
1456  CE => '1', -- Clock enable input
1457  CLK => CLK40, -- Clock input
1458  D => e_i(i) -- SRL data input
1459  );
1460  end generate shift_mux36_e;
1461 
1462  shift_mux36_f : for i in 0 to 35 generate
1463  SRLC32E_inst_12 : SRLC32E
1464  generic map (
1465  INIT => X"00000000")
1466  port map (
1467  Q => Open,
1468  Q31 => g_i(i), -- SRL cascaded data output
1469  A => (Others => '1'), -- Select input
1470  CE => '1', -- Clock enable input
1471  CLK => CLK40, -- Clock input
1472  D => f_i(i) -- SRL data input
1473  );
1474  end generate shift_mux36_f;
1475 
1476  ttc_parity_calc : entity infrastructure_lib.ttc_parity
1477  port map (
1478  ttc_data => q_i(11 downto 4) & q_i(35 downto 12),
1479  parity12 => parity12,
1480  parity32 => parity32
1481  );
1482 
1483 -- register ttc information signal selection for IOBs to Processor FPGAs
1484  pipe_gen : for i in 0 to 3 generate
1485  pipe_ttc : process(clk40)
1486  begin
1487  if clk40' event and clk40 = '1' then
1488  ttc_L1A_i(i) <= q_i(0);
1489  ttc_BCR_i(i) <= q_i(1);
1490  ttc_ECR_i(i) <= q_i(2);
1491  ttc_pr_rdout_i(i) <= q_i(3);
1492  ttc_ECRID_i(7+i*8 downto i*8) <= q_i(11 downto 4);
1493  ttc_L1ID_i(23+i*24 downto i*24) <= q_i(35 downto 12);
1494  ttc_dummy_i(5+i*6 downto i*6) <= q_i(17 downto 12);
1495  if q_i(0) = '1' then -- parity over ECRID and L1ID
1496  ttc_parity_i(i) <= parity32;
1497  else -- parity over BCN
1498  ttc_parity_i(i) <= parity12;
1499  end if;
1500  end if;
1501  end process;
1502  end generate pipe_gen;
1503 
1504  ttc_bcr_gen : for i in 0 to 3 generate
1505  bcr : OBUFDS
1506  port map(
1507  o => ttc_BCR_p(i),
1508  ob => ttc_BCR_n(i),
1509  i => ttc_BCR_i(i)
1510  );
1511 
1512  end generate;
1513 
1514  ttc_L1A_gen : for i in 0 to 3 generate
1515  L1A : OBUFDS
1516  port map(
1517  o => ttc_L1A_p(i),
1518  ob => ttc_L1A_n(i),
1519  i => ttc_L1A_i(i)
1520  );
1521 
1522  end generate;
1523 
1524  ttc_ecr_gen : for i in 0 to 3 generate
1525  ecr : OBUFDS
1526  port map(
1527  o => ttc_ECR_p(i),
1528  ob => ttc_ECR_n(i),
1529  i => ttc_ECR_i(i)
1530  );
1531 
1532  end generate;
1533 
1534  ttc_pr_rdout_gen : for i in 0 to 3 generate
1535  pr_rd : OBUFDS
1536  port map(
1537  o => ttc_pr_rdout_p(i),
1538  ob => ttc_pr_rdout_n(i),
1539  i => ttc_pr_rdout_i(i)
1540  );
1541 
1542  end generate;
1543 
1544 -- ECRID and L1ID LVCMOS
1545 
1546  ttc_info_F1 <= ttc_dummy_i(5 downto 0) & ttc_ECRID_i(7 downto 0) & ttc_L1ID_i(23 downto 0);
1547  ttc_info_F2 <= ttc_dummy_i(11 downto 6) & ttc_ECRID_i(15 downto 8) & ttc_L1ID_i(47 downto 24);
1548  ttc_info_F3 <= ttc_dummy_i(17 downto 12) & ttc_ECRID_i(23 downto 16) & ttc_L1ID_i(71 downto 48);
1549  ttc_info_F4 <= ttc_dummy_i(23 downto 18) & ttc_ECRID_i(31 downto 24) & ttc_L1ID_i(95 downto 72);
1550  ttc_parity_F1 <= ttc_parity_i(0);
1551  ttc_parity_F2 <= ttc_parity_i(1);
1552  ttc_parity_F3 <= ttc_parity_i(2);
1553  ttc_parity_F4 <= ttc_parity_i(3);
1554 
1555  backplane_reg : entity infrastructure_lib.backplane_registers
1556  port map (
1557  ipb_clk => ipb_clk,
1558  ipb_rst => rst_ipb,
1559  clk => clk40,
1560  rst => reset,
1561  ipb_in => ipbw(N_SLV_BACKPLANE),
1562  ipb_out => ipbr(N_SLV_BACKPLANE),
1563  ttc_info => q_i,
1564  aurora_status_1 => aurora_status_hub1,
1565  aurora_1_gt0_txctl => aurora_1_gt0_txctrl_i,
1566  aurora_1_gt1_txctl => aurora_1_gt1_txctrl_i,
1567  aurora_1_gt2_txctl => aurora_1_gt2_txctrl_i,
1568  aurora_1_gt3_txctl => aurora_1_gt3_txctrl_i,
1569  aurora_status_2 => aurora_status_hub2,
1570  aurora_2_gt0_txctl => aurora_2_gt0_txctrl_i,
1571  aurora_2_gt1_txctl => aurora_2_gt1_txctrl_i,
1572  aurora_2_gt2_txctl => aurora_2_gt2_txctrl_i,
1573  aurora_2_gt3_txctl => aurora_2_gt3_txctrl_i,
1574  control_xoff_bus => mgt_xoff_bus, -- Processor Number order, (7 downto 4) Input Data (3 downto 0) TOBs
1575  control_busy_bus => local_busy_bus, -- Processor Number order, (7 downto 4) Input Data (3 downto 0) TOBs
1576  processor_busy_bus => processor_busy_bus, -- Processor Number order, (7 downto 4) Input Data (3 downto 0) TOBs
1577  input_data_readout_control => input_data_readout_control
1578  );
1579 
1580 ---- mgt ipbus registers
1581 
1582  mgt_slaves : entity infrastructure_lib.mgt_cntrl_slaves
1583  port map (
1584  rx_clk160 => rx_clk160,
1585  rx_clk280 => rx_clk280,
1586  ipb_clk => ipb_clk,
1587  ipb_rst => rst_ipb,
1588  ipb_in => ipbw(N_SLV_CNTRL_MGT),
1589  ipb_out => ipbr(N_SLV_CNTRL_MGT),
1590  --mgt quad
1591  loopback => loopback,
1592  softreset_tx => softreset_tx,
1593  softreset_rx => softreset_rx,
1594  qpll_lock => qpll_lock,
1595  qpll_refclklost => qpll_refclklost,
1596  rx_resetdone => rx_resetdone,
1597  rx_fsm_resetdone => rx_fsm_resetdone,
1598  rx_byteisaligned => rx_byteisaligned,
1599  tx_resetdone => tx_resetdone,
1600  tx_fsm_resetdone => tx_fsm_resetdone,
1601  tx_bufstatus => tx_bufstatus,
1602  rx_realign => rx_realign,
1603  rx_disperr => rx_disperr,
1604  encode_error => encode_error,
1605  bc_reg_sel => bc_reg_sel,
1606  delay_cntr_0 => delay_cntr_0,
1607  delay_cntr_1 => delay_cntr_1,
1608  mux_sel => mux_sel,
1609  mgt_enable => mgt_enable,
1610  crc_error => crc_error_i
1611  );
1612 
1613 -- generate reset in 320 MHz domain from initial reset signal, TTC MGT not enabled or change in TTC enable...
1614 
1615  ttc_rst_clk40 : process(clk40)
1616  variable last_ttc_enable: std_logic:= '0';
1617  begin
1618  if rising_edge(clk40) then
1619  if (reset = '1') or (mgt_enable(0) = '0') or ((ttc_enable xor last_ttc_enable) = '1') then
1620 -- infer a toggle flip flop in source domain
1621  ttc_rst_tff <= not ttc_rst_tff;
1622  else
1623  ttc_rst_tff <= ttc_rst_tff;
1624  end if;
1625  last_ttc_enable := ttc_enable;
1626  end if;
1627  end process ttc_rst_clk40;
1628 
1629  ttc_rst_clk320 : process(clk320)
1630  begin
1631  if rising_edge(clk320) then
1632  rst_320_tff_buf <= rst_320_tff_buf(0) & ttc_rst_tff;
1633  end if;
1634  end process ttc_rst_clk320;
1635 
1636  reset_clk320 : process(clk320)
1637  Variable stretch: std_logic_vector(7 downto 0) := (Others => '1');
1638  begin
1639  if rising_edge(clk320) then
1640  if ((rst_320_tff_buf(1) xor rst_320_tff_buf(0)) = '1') then
1641  stretch := (Others => '1');
1642  else
1643  stretch := stretch(6 downto 0) & "0";
1644  end if;
1645  rst_320 <= stretch(7);
1646  end if;
1647  end process reset_clk320;
1648 
1649  rst_320_n <= not rst_320;
1650 
1651  clk_mgt_bus_gen : for i in 0 to N_PROCESSORFPGA*2 - 1 generate
1652  clk_mgt_bus(i) <= rx_clk280(i);
1653  end generate clk_mgt_bus_gen;
1654 
1655  readout_packet_block : entity work.packet_block
1656  generic map (
1657  NProcessorFPGA => N_PROCESSORFPGA,
1658  TOB_FIFO_ADDR_WIDTH => 13, -- size of TOB FIFO RAM in packet_fifo_block for each Processor FPGA
1659  MERGED_FIFO_ADDR_WIDTH => 13, -- size of merged FIFO RAMs after TOB merging
1660  RAW_FIFO_ADDR_WIDTH => 13, -- size of RAW FIFO RAM in packet_fifo_block for each Processor FPGA
1661  TOB_SPY_ADDR_WIDTH => 11, -- size of each Processor FPGA TOB SPY RAM inside mgt_buffer
1662  RAW_SPY_ADDR_WIDTH => 11, -- size of each Processor FPGA RAW SPY RAM inside mgt_buffer
1663  MERGER_SPY_ADDR_WIDTH => 10, -- NB DPRAM64 so IPBus address width is 1 more
1664  AURORA_SPY_ADDR_WIDTH => 12, -- NB DPRAM64 so IPBus address width is 1 more
1665  MAX_BUILT_PACKET_WIDTH => 9
1666  )
1667  port map (
1668 -- clocks
1669  clk40 => clk40,
1670  clk_mgt_bus => clk_mgt_bus,
1671  clk_320 => clk320,
1672  clk_ipb => ipb_clk,
1673  rst_ipb => rst_ipb,
1674  rst_320 => rst_320,
1675 -- Shelf Address and eFEX number
1676  eFEX_number(7 downto 4) => hardware_addr(11 downto 8),
1677  eFEX_number(3 downto 0) => efex_number,
1678 -- IPBus
1679  ipb_in => ipbw(N_SLV_DATA_PATH),
1680  ipb_out => ipbr(N_SLV_DATA_PATH),
1681 -- TTC data
1682  bcr_40 => hub1_combined_ttc(17), -- bunch counter reset
1683  ecr_40 => hub1_combined_ttc(18), -- event counter reset
1684  rst_ttc => ttc_fifo_reset,
1685  ttc_wr_en => hub1_combined_ttc(16), -- L1A strobe
1686  ttc_rd_en => q_i(0), -- delayed L1A strobe as defined by ftm_ttc_mode
1687  ttc_din => ttc_din,
1688 -- input and output control
1689  l1a_enable => l1a_enable,
1690  source_enable(3 downto 0)=> tob_ro_en,
1691  source_enable(7 downto 4)=> raw_ro_en,
1692  tob_destination_enable => tob_aurora_en,
1693  raw_destination_enable => raw_aurora_en,
1694 -- data from MGT
1695  data_from_mgt_bus => data_from_mgt_bus, -- first TOB then Input Data for each FPGA in turn in U number order
1696  char_is_k_bus => char_is_k_bus, -- first TOB then Input Data for each FPGA in turn in U number order
1697  error_from_mgt_bus => error_from_mgt_bus, -- first TOB then Input Data for each FPGA in turn in U number order
1698 -- data to Aurora
1699  payload_data_bus => payload_data_bus,
1700  payload_valid_bus => payload_valid_bus,
1701  payload_last_bus => payload_last_bus,
1702  tready_data_bus => tready_data_bus,
1703  packet_mux_source => packet_mux_source,
1704 -- flow control
1705  tob_xoff_bus => tob_xoff_bus,
1706  raw_xoff_bus => raw_xoff_bus,
1707  mgt_xoff_bus => mgt_xoff_bus,
1708  busy_bus => local_busy_bus
1709  );
1710 
1711  merged_busy_bus <= (local_busy_bus or processor_busy_bus) and (raw_ro_en & tob_ro_en);
1712 
1713  busy_status_block: process(ipb_clk)
1714  variable busy_status: std_logic_vector(15 downto 0);
1715  begin
1716  if rising_edge(ipb_clk) then
1717  busy_status := (processor_busy_bus and (raw_ro_en & tob_ro_en)) & (local_busy_bus and (raw_ro_en & tob_ro_en));
1718  if (aurora_en(0) = '1') then
1719  busy_status_hub1 <= busy_status;
1720  else
1721  busy_status_hub1 <= (Others => '0');
1722  end if;
1723  if (aurora_en(1) = '1') then
1724  busy_status_hub2 <= busy_status;
1725  else
1726  busy_status_hub2 <= (Others => '0');
1727  end if;
1728  end if;
1729  end process busy_status_block;
1730 
1731  hub1_axi_stream_fifo : axi_stream_fifo
1732  port map (
1733  wr_rst_busy => open,
1734  rd_rst_busy => rd_rst_busy_hub1,
1735  m_aclk => aurora_user_clk_hub1,
1736  s_aclk => clk320,
1737  s_aresetn => rst_320_n, -- Global reset: This signal is active-Low.
1738  s_axis_tvalid => payload_valid_bus(0),
1739  s_axis_tready => tready_data_bus(0),
1740  s_axis_tdata => payload_data_bus(0),
1741  s_axis_tkeep => (others => '0'),
1742  s_axis_tlast => payload_last_bus(0),
1743  s_axis_tuser => (others => '0'),
1744  m_axis_tvalid => s_axi_tx_tvalid_hub1,
1745  m_axis_tready => s_axi_tx_tready_vld_hub1,
1746  m_axis_tdata => s_axi_tx_tdata_data_hub1,
1747  m_axis_tkeep => s_axi_tx_tkeep_hub1,
1748  m_axis_tlast => s_axi_tx_tlast_hub1,
1749  m_axis_tuser => open
1750  );
1751 
1752  hub1_ufc_block : entity work.ufc_controller
1753  port map (
1754  clock => aurora_user_clk_hub1,
1755  reset => rd_rst_busy_hub1,
1756  enable => aurora_en(0),
1757  busy_tob => merged_busy_bus(3 downto 0),
1758  busy_raw => merged_busy_bus(7 downto 4),
1759  s_axi_tx_tready => s_axi_tx_tready_hub1,
1760  s_axi_ufc_tx_tready => s_axi_ufc_tx_ack_hub1,
1761  s_axi_ufc_tx_tvalid => s_axi_ufc_tx_req_hub1,
1762  s_axi_ufc_tx_tdata => s_axi_ufc_tx_ms_hub1,
1763  AXI_UFC_TDATA => s_axi_tx_tdata_ufc_hub1
1764  );
1765 
1766  s_axi_tx_tdata_hub1 <= s_axi_tx_tdata_data_hub1 when s_axi_tx_tready_hub1 = '1' else s_axi_tx_tdata_ufc_hub1;
1767 
1768  s_axi_tx_tready_vld_hub1 <= s_axi_tx_tready_hub1 and not rd_rst_busy_hub1;
1769 
1770  hub2_axi_stream_fifo : axi_stream_fifo
1771  port map (
1772  wr_rst_busy => open,
1773  rd_rst_busy => rd_rst_busy_hub2,
1774  m_aclk => aurora_user_clk_hub2,
1775  s_aclk => clk320,
1776  s_aresetn => rst_320_n, -- Global reset: This signal is active-Low.
1777  s_axis_tvalid => payload_valid_bus(1),
1778  s_axis_tready => tready_data_bus(1),
1779  s_axis_tdata => payload_data_bus(1),
1780  s_axis_tkeep => (others => '0'),
1781  s_axis_tlast => payload_last_bus(1),
1782  s_axis_tuser => (others => '0'),
1783  m_axis_tvalid => s_axi_tx_tvalid_hub2,
1784  m_axis_tready => s_axi_tx_tready_vld_hub2,
1785  m_axis_tdata => s_axi_tx_tdata_data_hub2,
1786  m_axis_tkeep => s_axi_tx_tkeep_hub2,
1787  m_axis_tlast => s_axi_tx_tlast_hub2,
1788  m_axis_tuser => open
1789  );
1790 
1791  hub2_ufc_block : entity work.ufc_controller
1792  port map (
1793  clock => aurora_user_clk_hub2,
1794  reset => rd_rst_busy_hub2,
1795  enable => aurora_en(1),
1796  busy_tob => merged_busy_bus(3 downto 0),
1797  busy_raw => merged_busy_bus(7 downto 4),
1798  s_axi_tx_tready => s_axi_tx_tready_hub2,
1799  s_axi_ufc_tx_tready => s_axi_ufc_tx_ack_hub2,
1800  s_axi_ufc_tx_tvalid => s_axi_ufc_tx_req_hub2,
1801  s_axi_ufc_tx_tdata => s_axi_ufc_tx_ms_hub2,
1802  AXI_UFC_TDATA => s_axi_tx_tdata_ufc_hub2
1803  );
1804 
1805  s_axi_tx_tdata_hub2 <= s_axi_tx_tdata_data_hub2 when s_axi_tx_tready_hub2 = '1' else s_axi_tx_tdata_ufc_hub2;
1806 
1807  s_axi_tx_tready_vld_hub2 <= s_axi_tx_tready_hub2 and not rd_rst_busy_hub2;
1808 
1809 -- payload_channel1_ila : ila_0
1810 -- port map (
1811 -- clk => clk320,
1812 -- probe0(63 downto 0) => payload_data_bus(0),
1813 -- probe0(64) => payload_valid_bus(0),
1814 -- probe0(65) => payload_last_bus(0),
1815 -- probe0(66) => tready_data_bus(0),
1816 -- probe0(69 downto 67) => packet_mux_source(2 downto 0)
1817 -- );
1818 
1819 -- payload_channel2_ila : ila_0
1820 -- port map (
1821 -- clk => clk320,
1822 -- probe0(63 downto 0) => payload_data_bus(1),
1823 -- probe0(64) => payload_valid_bus(1),
1824 -- probe0(65) => payload_last_bus(1),
1825 -- probe0(66) => tready_data_bus(1),
1826 -- probe0(69 downto 67) => packet_mux_source(6 downto 4)
1827 -- );
1828 
1829  output_channel1_ila : ila_0
1830  port map (
1831  clk => aurora_user_clk_hub1,
1832  probe0(63 downto 0) => s_axi_tx_tdata_hub1,
1833  probe0(64) => s_axi_tx_tvalid_hub1,
1834  probe0(65) => s_axi_tx_tlast_hub1,
1835  probe0(66) => s_axi_tx_tready_hub1,
1836  probe0(67) => s_axi_ufc_tx_req_hub1,
1837  probe0(68) => s_axi_ufc_tx_ack_hub1,
1838  probe0(69) => '0'
1839  );
1840 
1841  output_channel2_ila : ila_0
1842  port map (
1843  clk => aurora_user_clk_hub2,
1844  probe0(63 downto 0) => s_axi_tx_tdata_hub2,
1845  probe0(64) => s_axi_tx_tvalid_hub2,
1846  probe0(65) => s_axi_tx_tlast_hub2,
1847  probe0(66) => s_axi_tx_tready_hub2,
1848  probe0(67) => s_axi_ufc_tx_req_hub2,
1849  probe0(68) => s_axi_ufc_tx_ack_hub2,
1850  probe0(69) => '0'
1851  );
1852 
1853 --------------------------------------------------------------------------------------------------------------------------------------------
1854 -- Aurora hub1 connections
1855 --------------------------------------------------------------------------------------------------------------------------------------
1856  top_aurora_hub1 : entity infrastructure_lib.aurora_hub2
1857 
1858  port map (
1859  -- TX Stream Interface
1860  s_axi_tx_tdata => s_axi_tx_tdata_hub1,
1861  s_axi_tx_tvalid => s_axi_tx_tvalid_hub1,
1862  s_axi_tx_tready => s_axi_tx_tready_hub1,
1863  s_axi_tx_tkeep => s_axi_tx_tkeep_hub1,
1864  s_axi_tx_tlast => s_axi_tx_tlast_hub1,
1865  -- User Flow Control TX Interface
1866  s_axi_ufc_tx_req => s_axi_ufc_tx_req_hub1,
1867  s_axi_ufc_tx_ms => s_axi_ufc_tx_ms_hub1,
1868  s_axi_ufc_tx_ack => s_axi_ufc_tx_ack_hub1,
1869  -- V7 Serial I/O
1870  txp => aurora_hub1_txp,
1871  txn => aurora_hub1_txn,
1872  -- GT Reference Clock Interface
1873 
1874  gt_refclk1_p => aurora_hub1_refclk1_p, --aurora_refclk1_p,
1875  gt_refclk1_n => aurora_hub1_refclk1_n, --aurora_refclk1_n,
1876  -- Error Detection Interface
1877  tx_hard_err => tx_hard_err_hub1,
1878  -- Status
1879  tx_channel_up => tx_channel_up_hub1,
1880  tx_lane_up => tx_lane_up_hub1,
1881  -- txctrl
1882  aurora_gt0_txctrl => aurora_1_gt0_txctrl_i,
1883  aurora_gt1_txctrl => aurora_1_gt1_txctrl_i,
1884  aurora_gt2_txctrl => aurora_1_gt2_txctrl_i,
1885  aurora_gt3_txctrl => aurora_1_gt3_txctrl_i,
1886  -- System Interface
1887  user_clk_out => aurora_user_clk_hub1,
1888  sys_reset_out => sys_reset_out_hub1,
1889  tx_lock => tx_lock_hub1,
1890  init_clk => mac_clk,
1891  init_clk_out => init_clk_out_hub1,
1892  pll_not_locked => pll_not_locked_hub1,
1893  tx_resetdone => aurora_tx_resetdone_hub1,
1894  link_reset => link_reset_hub1
1895  );
1896 
1897  aurora_status_hub1 <= busy_status_hub1 & aurora_en(0) & hub1_combined_ttc_valid & hub1_combined_ttc(104) & hub1_combined_ttc(100) & hub1_combined_ttc(96) & hub1_combined_ttc(9) & hub1_combined_ttc(8) & aurora_tx_resetdone_hub1 & tx_lock_hub1 & pll_not_locked_hub1 & tx_hard_err_hub1 & tx_channel_up_hub1 & tx_lane_up_hub1;
1898 
1899 --------------------------------------------------------------------------------------------------------------------------------------------
1900 -- Aurora hub2 connections
1901 --------------------------------------------------------------------------------------------------------------------------------------
1902  top_aurora_hub2 : entity infrastructure_lib.aurora_hub2
1903 
1904  port map (
1905  -- TX Stream Interface
1906  s_axi_tx_tdata => s_axi_tx_tdata_hub2,
1907  s_axi_tx_tvalid => s_axi_tx_tvalid_hub2,
1908  s_axi_tx_tready => s_axi_tx_tready_hub2,
1909  s_axi_tx_tkeep => s_axi_tx_tkeep_hub2,
1910  s_axi_tx_tlast => s_axi_tx_tlast_hub2,
1911  -- User Flow Control TX Interface
1912  s_axi_ufc_tx_req => s_axi_ufc_tx_req_hub2,
1913  s_axi_ufc_tx_ms => s_axi_ufc_tx_ms_hub2,
1914  s_axi_ufc_tx_ack => s_axi_ufc_tx_ack_hub2,
1915  -- V7 Serial I/O
1916  txp => aurora_hub2_txp,
1917  txn => aurora_hub2_txn,
1918  -- GT Reference Clock Interface
1919 
1920  gt_refclk1_p => aurora_hub2_refclk1_p, --aurora_refclk1_p,
1921  gt_refclk1_n => aurora_hub2_refclk1_n, --aurora_refclk1_n,
1922  -- Error Detection Interface
1923  tx_hard_err => tx_hard_err_hub2,
1924  -- Status
1925  tx_channel_up => tx_channel_up_hub2,
1926  tx_lane_up => tx_lane_up_hub2,
1927  -- txctrl
1928  aurora_gt0_txctrl => aurora_2_gt0_txctrl_i,
1929  aurora_gt1_txctrl => aurora_2_gt1_txctrl_i,
1930  aurora_gt2_txctrl => aurora_2_gt2_txctrl_i,
1931  aurora_gt3_txctrl => aurora_2_gt3_txctrl_i,
1932  -- System Interface
1933  user_clk_out => aurora_user_clk_hub2,
1934  sys_reset_out => sys_reset_out_hub2,
1935  tx_lock => tx_lock_hub2,
1936  init_clk => mac_clk,
1937  init_clk_out => init_clk_out_hub2,
1938  pll_not_locked => pll_not_locked_hub2,
1939  tx_resetdone => aurora_tx_resetdone_hub2,
1940  link_reset => link_reset_hub2
1941  );
1942 
1943  aurora_status_hub2 <= busy_status_hub2 & aurora_en(1) & hub2_combined_ttc_valid & hub2_combined_ttc(104) & hub2_combined_ttc(100) & hub2_combined_ttc(96) & hub2_combined_ttc(9) & hub2_combined_ttc(8) & aurora_tx_resetdone_hub2 & tx_lock_hub2 & pll_not_locked_hub2 & tx_hard_err_hub2 & tx_channel_up_hub2 & tx_lane_up_hub2;
1944 
1945  end generate;
1946 
1947 end Spec;
aurora_hub2
Definition: aurora_hub2.vhd:29
backplane_registers
Definition: backplane_registers.vhd:19
backplane_registers.input_data_readout_control
out input_data_readout_control std_logic_vector( 31 downto 0)
Privileged readout control.
Definition: backplane_registers.vhd:53
backplane_registers.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: backplane_registers.vhd:24
backplane_registers.aurora_status_1
in aurora_status_1 std_logic_vector( 31 downto 0)
aurora status hub1
Definition: backplane_registers.vhd:36
backplane_registers.clk
in clk std_logic
TTC fabric clock.
Definition: backplane_registers.vhd:26
backplane_registers.control_xoff_bus
in control_xoff_bus std_logic_vector( 7 downto 0)
XOff and BUSY.
Definition: backplane_registers.vhd:48
backplane_registers.aurora_status_2
in aurora_status_2 std_logic_vector( 31 downto 0)
aurora status hub2
Definition: backplane_registers.vhd:42
backplane_registers.ipb_clk
in ipb_clk std_logic
ipbus clock
Definition: backplane_registers.vhd:22
backplane_registers.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: backplane_registers.vhd:32
backplane_registers.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: backplane_registers.vhd:30
backplane_registers.rst
in rst std_logic
fabric reset
Definition: backplane_registers.vhd:28
backplane_registers.ttc_info
in ttc_info std_logic_vector( 35 downto 0)
ttc_L1ID & ttc_ECRID & ttc_pr_rdout & ttc_ECR & ttc_BCR & ttc_L1A
Definition: backplane_registers.vhd:34
clocks_7s_extphy
Definition: clocks_7s_extphy.vhd:23
cntrl_crc_checker
Definition: cntrl_crc_checker.vhd:13
cntrl_crc_checker.reset
in reset std_logic
reset
Definition: cntrl_crc_checker.vhd:18
cntrl_crc_checker.clk
in clk std_logic
MGT rx clock of 160MHz.
Definition: cntrl_crc_checker.vhd:16
cntrl_crc_checker.mgt_enable
in mgt_enable std_logic
mgt_enbable
Definition: cntrl_crc_checker.vhd:20
cntrl_crc_checker.mgt_commdet
in mgt_commdet std_logic
MGT commadet.
Definition: cntrl_crc_checker.vhd:22
cntrl_crc_checker.rxdata
in rxdata std_logic_vector( 31 downto 0)
MGT rx data.
Definition: cntrl_crc_checker.vhd:24
cntrl_crc_checker.crc_error
out crc_error std_logic
crc error
Definition: cntrl_crc_checker.vhd:28
common_id_registers
FPGA Common ID Module.
Definition: common_id_registers.vhd:49
common_id_registers.fw_version
in fw_version std_logic_vector( 31 downto 0)
Version of the repository (format: MMmmcccc in hex)
Definition: common_id_registers.vhd:66
common_id_registers.xml_Gitsha
in xml_Gitsha std_logic_vector( 31 downto 0)
Short 7-digit git SHA of the XMLs.
Definition: common_id_registers.vhd:64
common_id_registers.ipb_rst
in ipb_rst std_logic
ipbus reset
Definition: common_id_registers.vhd:54
common_id_registers.fw_Gitsha
in fw_Gitsha std_logic_vector( 31 downto 0)
Short 7-digit git SHA of the repository.
Definition: common_id_registers.vhd:68
common_id_registers.Module_ID
in Module_ID std_logic_vector( 31 downto 0)
module id of the eFEX
Definition: common_id_registers.vhd:60
common_id_registers.build_date
in build_date std_logic_vector( 31 downto 0)
Date format DDMMYYYY in decimal.
Definition: common_id_registers.vhd:70
common_id_registers.build_time
in build_time std_logic_vector( 31 downto 0)
Time format 00HHMMSS in decimal.
Definition: common_id_registers.vhd:74
common_id_registers.ipb_clk
in ipb_clk std_logic
ipbus clk of 31.25MHz
Definition: common_id_registers.vhd:52
common_id_registers.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to m.
Definition: common_id_registers.vhd:58
common_id_registers.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: common_id_registers.vhd:56
common_id_registers.xml_version
in xml_version std_logic_vector( 31 downto 0)
Version of the XMLs.
Definition: common_id_registers.vhd:62
eth_7s_gmii
Definition: eth_7s_gmii.vhd:17
golden
Definition: golden.vhd:5
infrastructure_slaves_cntrl
control fpga infrastructure slaves
Definition: infrastructure_slaves_cntrl.vhd:24
infrastructure_slaves_cntrl.pll_le
out pll_le std_logic
spi pll enable enable
Definition: infrastructure_slaves_cntrl.vhd:47
infrastructure_slaves_cntrl.pll_mosi
out pll_mosi std_logic
spi pll output signals
Definition: infrastructure_slaves_cntrl.vhd:51
infrastructure_slaves_cntrl.ipb_rst
in ipb_rst std_logic
IPBus Reset input.
Definition: infrastructure_slaves_cntrl.vhd:29
infrastructure_slaves_cntrl.flash_le
out flash_le std_logic
spi flash enable
Definition: infrastructure_slaves_cntrl.vhd:57
infrastructure_slaves_cntrl.control_reg
out control_reg std_logic_vector( 31 downto 0)
module control signals
Definition: infrastructure_slaves_cntrl.vhd:37
infrastructure_slaves_cntrl.flash_miso
in flash_miso std_logic
spi flash input signals
Definition: infrastructure_slaves_cntrl.vhd:55
infrastructure_slaves_cntrl.status
in status std_logic_vector( 31 downto 0)
module status signals
Definition: infrastructure_slaves_cntrl.vhd:35
infrastructure_slaves_cntrl.pll_clko
out pll_clko std_logic
spi pll clock
Definition: infrastructure_slaves_cntrl.vhd:49
infrastructure_slaves_cntrl.ipb_clk
in ipb_clk std_logic
IPBus clock.
Definition: infrastructure_slaves_cntrl.vhd:27
infrastructure_slaves_cntrl.flash_clko
out flash_clko std_logic
spi flash clock
Definition: infrastructure_slaves_cntrl.vhd:59
infrastructure_slaves_cntrl.scl
out scl std_logic
i2c bus signals
Definition: infrastructure_slaves_cntrl.vhd:41
infrastructure_slaves_cntrl.ipb_out
out ipb_out ipb_rbus
IPBus output bus going from slaves to master.
Definition: infrastructure_slaves_cntrl.vhd:33
infrastructure_slaves_cntrl.pll_miso
in pll_miso std_logic
spi pll input signals
Definition: infrastructure_slaves_cntrl.vhd:45
infrastructure_slaves_cntrl.pll_select
out pll_select std_logic_vector( 1 downto 0)
spi pll select
Definition: infrastructure_slaves_cntrl.vhd:53
infrastructure_slaves_cntrl.flash_mosi
out flash_mosi std_logic
spi flash output signals
Definition: infrastructure_slaves_cntrl.vhd:61
infrastructure_slaves_cntrl.ipb_in
in ipb_in ipb_wbus
IPBus input bus going from master to slaves.
Definition: infrastructure_slaves_cntrl.vhd:31
interconnect
Top ipbus interconnection.
Definition: interconnect_struct.vhd:15
interconnect.rx_data
out rx_data std_logic_vector( 8 DOWNTO 0)
slave_rx_data
Definition: interconnect_struct.vhd:31
interconnect.mac_clk
in mac_clk std_logic
clock 125 MHz
Definition: interconnect_struct.vhd:18
interconnect.master_rx_data
in master_rx_data std_logic_vector( 9 DOWNTO 0)
IPBUS signals of master rx_data from control FPGA.
Definition: interconnect_struct.vhd:20
interconnect.tx_data
in tx_data std_logic_vector( 8 DOWNTO 0)
slave_tx_data
Definition: interconnect_struct.vhd:24
interconnect.master_rx_err
out master_rx_err std_logic
parity error
Definition: interconnect_struct.vhd:26
interconnect.rst_macclk
in rst_macclk std_logic
macclk Reset input
Definition: interconnect_struct.vhd:22
interconnect.process_tx_data
out process_tx_data std_logic_vector( 9 DOWNTO 0)
master_tx_data
Definition: interconnect_struct.vhd:28
ipbus_decode_L1CaloEfex
Definition: ipbus_decode_L1CaloEfex.vhd:14
mgt_cntrl_slaves
MGT ipbus slave for control FPGA.
Definition: mgt_cntrl_slaves.vhd:26
mgt_type
Definition: mgt_type_pkg.vhd:4
nreset_pll
Reset PLLs.
Definition: nreset_pll.vhd:12
nreset_pll.enable_pll_rst
in enable_pll_rst std_logic
pll reset enable
Definition: nreset_pll.vhd:17
nreset_pll.SYNC_B_CDCE
out SYNC_B_CDCE std_logic
pll synch_b_CDCE
Definition: nreset_pll.vhd:23
packet_block
Instantiate the readout merging and routing logic...
Definition: packet_block.vhd:43
packet_mux_type
Definition: packet_mux_type.vhd:4
pll_selector
PLL enable for the control FPGA.
Definition: pll_selector.vhd:10
pll_selector.sel
in sel STD_LOGIC_VECTOR( 1 downto 0)
selector bits
Definition: pll_selector.vhd:13
pll_selector.pll_en_1
out pll_en_1 STD_LOGIC
enable pll 1
Definition: pll_selector.vhd:15
pll_selector.pll_en
in pll_en STD_LOGIC
pll enable
Definition: pll_selector.vhd:19
pll_selector.pll_en_3
out pll_en_3 STD_LOGIC
enable pll 3
Definition: pll_selector.vhd:17
reconfig
FPGA Reconfiguration State Machine.
Definition: reconfig.vhd:25
reconfig.WBSTAR
in WBSTAR std_logic_vector( 31 downto 0)
Warm Boot Start Address.
Definition: reconfig.vhd:29
startup
Startup Block.
Definition: startup.vhd:15
top_cntrl_synch
Top Synchronisation of the control FPGA.
Definition: top_ctrl_synch.vhd:19
top_cntrl_synch.delay_num
out delay_num std_logic_vector( 3 downto 0)
counted delay on the first stage of the synchronisation
Definition: top_ctrl_synch.vhd:37
top_cntrl_synch.reset
in reset std_logic
reset active high
Definition: top_ctrl_synch.vhd:27
top_cntrl_synch.rx_resetdone
in rx_resetdone std_logic
rx reset done of the MGT
Definition: top_ctrl_synch.vhd:41
top_cntrl_synch.MGT_Commadet
in MGT_Commadet std_logic
comma detected for incoming data
Definition: top_ctrl_synch.vhd:31
top_cntrl_synch.mux_sel
in mux_sel std_logic_vector( 3 downto 0)
setting the first stage mux
Definition: top_ctrl_synch.vhd:35
top_cntrl_synch.data_out
out data_out std_logic_vector( 128 downto 0)
data out of 128 bits
Definition: top_ctrl_synch.vhd:45
top_cntrl_synch.reg128_latch
out reg128_latch std_logic
latch enable
Definition: top_ctrl_synch.vhd:43
top_cntrl_synch.data_in
in data_in std_logic_vector( 31 downto 0)
rx data in
Definition: top_ctrl_synch.vhd:47
top_cntrl_synch.start
in start std_logic
start pulse for the calibration to start
Definition: top_ctrl_synch.vhd:39
top_cntrl_synch.crc_error_in
in crc_error_in std_logic
crc_error input
Definition: top_ctrl_synch.vhd:50
top_cntrl_synch.enable_mgt
in enable_mgt std_logic
enable mgt rx register
Definition: top_ctrl_synch.vhd:29
top_cntrl_synch.TTC_clk
in TTC_clk std_logic
ttc clk of 40MHz
Definition: top_ctrl_synch.vhd:25
top_cntrl_synch.reg_sel
in reg_sel std_logic_vector( 3 downto 0)
setting BC mux
Definition: top_ctrl_synch.vhd:33
top_cntrl_synch.rx_clk160
in rx_clk160 std_logic
rx clock of the mgt
Definition: top_ctrl_synch.vhd:23
top_efex_control.spec
This is the top level of the Control FPGA.
Definition: top_efex_control.vhd:182
pr_rd
obufds pr_rdpr_rd
ttc privilage read out fanout to the process fpgas
Definition: top_efex_control.vhd:1540
bcr
obufds bcrbcr
ttc bcr fanout to the process fpgas
Definition: top_efex_control.vhd:1510
ecr
obufds ecrecr
ttc ecr fanout to the process fpgas
Definition: top_efex_control.vhd:1530
top_efex_control
This is the top level of the Control FPGA.
Definition: top_efex_control.vhd:70
top_efex_control.INFRASTRUCTURE_LIB_SHA
INFRASTRUCTURE_LIB_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA.
Definition: top_efex_control.vhd:104
top_efex_control.IPBUS_LIB_VER
IPBUS_LIB_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the readout library (format: MMmmpppp in hex)
Definition: top_efex_control.vhd:108
top_efex_control.CON_SHA
CON_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the Hog submodule.
Definition: top_efex_control.vhd:98
top_efex_control.TOP_VER
TOP_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the top folder, see TOP_SHA.
Definition: top_efex_control.vhd:91
top_efex_control.GLOBAL_SHA
GLOBAL_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the repository.
Definition: top_efex_control.vhd:79
top_efex_control.TOP_SHA
TOP_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the top folder: list file, xdcs, XMLs, tcl file and this file.
Definition: top_efex_control.vhd:89
top_efex_control.GLOBAL_TIME
GLOBAL_TIME std_logic_vector( 31 downto 0) := x"00000000"
Time format 00HHMMSS in decimal.
Definition: top_efex_control.vhd:77
top_efex_control.GLOBAL_VER
GLOBAL_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the repository (format: MMmmcccc in hex)
Definition: top_efex_control.vhd:81
top_efex_control.GLOBAL_DATE
GLOBAL_DATE std_logic_vector( 31 downto 0) := x"00000000"
Date format DDMMYYYY in decimal.
Definition: top_efex_control.vhd:75
top_efex_control.HOG_SHA
HOG_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the Hog submodule.
Definition: top_efex_control.vhd:94
top_efex_control.N_PROCESSORFPGA
N_PROCESSORFPGA positive := 4
number of Processor FPGA instantiated in top_mgt_cfgpa
Definition: top_efex_control.vhd:110
top_efex_control.INFRASTRUCTURE_LIB_VER
INFRASTRUCTURE_LIB_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of infrastructure library (format: MMmmcccc in hex)
Definition: top_efex_control.vhd:102
top_efex_control.XML_VER
XML_VER std_logic_vector( 31 downto 0) := x"00000000"
Version of the XMLs.
Definition: top_efex_control.vhd:86
top_efex_control.FLAVOUR
FLAVOUR integer := 0
Integer used to distinguish different FPGAs having a slightly different firmware.
Definition: top_efex_control.vhd:73
top_efex_control.XML_SHA
XML_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the XMLs.
Definition: top_efex_control.vhd:84
top_efex_control.IPBUS_LIB_SHA
IPBUS_LIB_SHA std_logic_vector( 31 downto 0) := x"00000000"
Short 7-digit git SHA of the ipbus submodule.
Definition: top_efex_control.vhd:106
top_mgt_cfpga
Top MGT cFPGA.
Definition: top_mgt_cfpga.vhd:23
top_mgt_cfpga.hub1_rx_data
out hub1_rx_data std_logic_vector( 31 downto 0)
rx data from ttc information gt0
Definition: top_mgt_cfpga.vhd:84
top_mgt_cfpga.rx_resetdone
out rx_resetdone std_logic_vector( 11 downto 0)
rx reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:48
top_mgt_cfpga.clk40
in clk40 std_logic
clk40 generatred from ttc clock
Definition: top_mgt_cfpga.vhd:31
top_mgt_cfpga.rx_disperr
out rx_disperr std_logic_vector( 47 downto 0)
rx_disperr of the all of the MGTs
Definition: top_mgt_cfpga.vhd:62
top_mgt_cfpga.rx_clk160
out rx_clk160 std_logic_vector( 3 downto 0)
rx clock 160MHz
Definition: top_mgt_cfpga.vhd:37
top_mgt_cfpga.tx_fsm_resetdone
out tx_fsm_resetdone std_logic_vector( 11 downto 0)
tx fsm reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:56
top_mgt_cfpga.error_from_mgt_bus
out error_from_mgt_bus std_logic_vector( NProcessorFPGA* 2- 1 downto 0)
error from the MGT links of 11.2Gbps
Definition: top_mgt_cfpga.vhd:82
top_mgt_cfpga.rx_fsm_resetdone
out rx_fsm_resetdone std_logic_vector( 11 downto 0)
rx fsm reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:50
top_mgt_cfpga.char_is_k_bus
out char_is_k_bus std_logic_vector( NProcessorFPGA* 2- 1 downto 0)
k char from process fpgas
Definition: top_mgt_cfpga.vhd:80
top_mgt_cfpga.encode_error
out encode_error std_logic_vector( 47 downto 0)
encode_error of the all of the MGTs
Definition: top_mgt_cfpga.vhd:64
top_mgt_cfpga.mgt_QPLLLOCK_OUT
out mgt_QPLLLOCK_OUT std_logic_vector( 2 downto 0)
mgt_QPLLLOCK_OUT
Definition: top_mgt_cfpga.vhd:74
top_mgt_cfpga.mgt_QPLLREFCLKLOST_OUT
out mgt_QPLLREFCLKLOST_OUT std_logic_vector( 2 downto 0)
mgt_QPLLREFCLKLOST_OUT
Definition: top_mgt_cfpga.vhd:76
top_mgt_cfpga.hub2_rx_data
out hub2_rx_data std_logic_vector( 31 downto 0)
rx data from gt1
Definition: top_mgt_cfpga.vhd:87
top_mgt_cfpga.clk160
in clk160 std_logic
clk160 generatred from ttc clock
Definition: top_mgt_cfpga.vhd:33
top_mgt_cfpga.tx_resetdone
out tx_resetdone std_logic_vector( 11 downto 0)
tx reset done of the all of the MGTs
Definition: top_mgt_cfpga.vhd:54
top_mgt_cfpga.loopback
in loopback std_logic_vector( 5 downto 0)
loopback
Definition: top_mgt_cfpga.vhd:68
top_mgt_cfpga.mgt_SOFT_RESET_TX_IN
in mgt_SOFT_RESET_TX_IN std_logic_vector( 2 downto 0)
soft reset of tx quad
Definition: top_mgt_cfpga.vhd:70
top_mgt_cfpga.Q_CLK_GTREFCLK_PAD_N_IN
in Q_CLK_GTREFCLK_PAD_N_IN std_logic_vector( 2 downto 0)
clock input to the quad
Definition: top_mgt_cfpga.vhd:39
top_mgt_cfpga.RXN_IN
in RXN_IN std_logic_vector( 11 downto 0)
rx quad input
Definition: top_mgt_cfpga.vhd:42
top_mgt_cfpga.mgt_SOFT_RESET_RX_IN
in mgt_SOFT_RESET_RX_IN std_logic_vector( 2 downto 0)
soft reset of rx quad
Definition: top_mgt_cfpga.vhd:72
top_mgt_cfpga.start
in start std_logic
start
Definition: top_mgt_cfpga.vhd:29
top_mgt_cfpga.rx_realign
out rx_realign std_logic_vector( 11 downto 0)
rx_realign of the all of the MGTs
Definition: top_mgt_cfpga.vhd:60
top_mgt_cfpga.data_from_mgt_bus
out data_from_mgt_bus mgt_data_array( NProcessorFPGA* 2- 1 downto 0)
rx data from process fpgas
Definition: top_mgt_cfpga.vhd:78
top_mgt_cfpga.rx_clk280
out rx_clk280 std_logic_vector( 7 downto 0)
rx clock 280MHz
Definition: top_mgt_cfpga.vhd:35
top_mgt_cfpga.TXN_OUT
out TXN_OUT std_logic_vector( 11 downto 0)
tx quad input
Definition: top_mgt_cfpga.vhd:45
top_mgt_cfpga.tx_bufstatus
out tx_bufstatus std_logic_vector( 23 downto 0)
tx_bufstatus of the all of the MGTs
Definition: top_mgt_cfpga.vhd:58
top_mgt_cfpga.mgt_commadret
out mgt_commadret std_logic_vector( 1 downto 0)
mgt_commadret
Definition: top_mgt_cfpga.vhd:66
top_mgt_cfpga.rx_byteisaligned
out rx_byteisaligned std_logic_vector( 11 downto 0)
rx_byteisaligned of the all of the MGTs
Definition: top_mgt_cfpga.vhd:52
top_udp_config_FPGA
Definition: top_udp_config_fpga_struct.vhd:16
ttc_parity
generate parity for data going from Control FPGA to Processors
Definition: ttc_parity.vhd:13
ufc_controller
UFC_block...
Definition: ufc_controller.vhd:16
Generated on Tue Nov 11 2025 09:44:32 for eFEX firmware by   doxygen 1.9.1