top_efex_control.vhd File Reference

This is the top level of the Control FPGA. More...

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Entities
top_efex_control	entity
	This is the top level of the Control FPGA. More...
spec	architecture
	This is the top level of the Control FPGA. More...

Detailed Description

This is the top level of the Control FPGA.

Overview

The Control FPGA implements logic in three main functional areas:

• the real-time interface to the TTC
• the readout path
• the slow-control interface of the eFEX including support for the IPBus endpoints on the Processor FPGAs

Real-Time Logic

The TTC 40 MHz clock is received on a dedicated backplane channel, with the TTC information encoded on a second channel in the L1Calo backplane format. In terms of the TTC interface, the Control FPGA implements the following:

• It receives the data over one 6.4 Gb/s MGT link from the Hub module with fixed latency (the 6G4 part of top_mgt_cfpga) using the same first level synchronisation scheme as the Processor FPGAs (top_cntrl_synch)
• It decodes this TTC data and transmits the L1A, BCR, BCR, privileged readout, ECRID and L1ID signals synchronously as 40 MHz parallel signals to the processor FPGAs and buffers this information for use by the readout logic.

Readout Path

On the readout path, the Control FPGA performs the following functions:

• It receives TOB and calorimeter data from the four Processor FPGAs via a total of eight streams of 11.2 Gb/s data (the 11G2 part of top_mgt_cfpga)

The bulk of the readout logic is in packet_block:

• It buffers these data for flow control. (The main readout buffers on the eFEX are on the Processor FPGA. Correspondingly, the RAM resources required here are less than half of those on the Processor FPGAs).
• For the TOB readout it combines all of the data for an event into a single packet, for the Input Data the data for each FPGA remains in separate packets, then for each packet it adds header and trailer words that include TTC information and CRCs

Finally it sends the resultant packet to the L1Calo ROD via the Aurora interfaces that combine four 6.4Gb/s MGT lanes into a single channel to each ROD (aurora_hub2)

All of the above is under the control of a state machine which responds to back pressure from the L1Calo RODs, and can assert it to the Processor FPGAs and if need be assert BUSY.

Slow control and IPBus infrastructure

The control interface is implemented using IP from the IPBus project, which provides access to registers and RAM space within the firmware. For documentation on IPBus, see https://ipbus.web.cern.ch/introduction/

The IPBus infrastructure consists of:

• The Ethernet MAC clocks_7s_extphy and eth_7s_gmii (the Control FPGA is the only FPGA on the eFEX that has a physical connection to the Ethernet)
• top_udp_config_FPGA and interconnect (IPBus link layer to Processor FPGAs and local IPBus bus master on Control FPGA)

The local IPBus bus master interfaces to the following modules:

• common_id_registers (ID registers)
• infrastructure_slaves_cntrl (I2C and SPI interfaces)
• aurora_registers (control and status registers for the Aurora interface to the Hub-ROD)
• startup (Xilinx IP that provides a user interface FPGA configuration logic)
• self_configure (FPGA re-configuration control)
• pll_selector (generates PLL enable signals according to input selected)
• nreset_pll (generates reset for PLL)

  Author

  Mohammed Siyad

  David Sankey

Definition in file top_efex_control.vhd.