pll_selector Entity Reference

PLL enable for the control FPGA. More...

Inheritance diagram for pll_selector:

Entities
Behavioral	architecture
	PLL enable for the control FPGA. More...

Libraries
IEEE

Use Clauses
STD_LOGIC_1164

Ports
sel	in	STD_LOGIC_VECTOR ( 1 downto 0 )
		selector bits
pll_en_1	out	STD_LOGIC
		enable pll 1
pll_en_3	out	STD_LOGIC
		enable pll 3
pll_en	in	STD_LOGIC
		pll enable

Detailed Description

PLL enable for the control FPGA.

This is PLL enable selector mux that is controlled through IPbus

Author

Mohammed Siyad

Definition at line 10 of file pll_selector.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/cntrl_slaves/pll_selector.vhd