official/Doc/pll__selector_8vhd_source.html

 library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;

 entity pll_selector is

     Port (

            sel : in STD_LOGIC_VECTOR (1 downto 0);

            pll_en_1 : out STD_LOGIC;

            pll_en_3 : out STD_LOGIC;

            pll_en : in STD_LOGIC);

 end pll_selector;

 architecture Behavioral of pll_selector is


 begin


     pll_en_1 <= pll_en when sel = "00" else '1';

     pll_en_3 <= pll_en when sel = "10" else '1';


 end Behavioral;

pll_selector.Behavioral
PLL enable for the control FPGA.
Definition: pll_selector.vhd:22

pll_selector
PLL enable for the control FPGA.
Definition: pll_selector.vhd:10

pll_selector.sel
in sel STD_LOGIC_VECTOR( 1 downto  0)
selector bits
Definition: pll_selector.vhd:13

pll_selector.pll_en_1
out pll_en_1 STD_LOGIC
enable pll 1
Definition: pll_selector.vhd:15

pll_selector.pll_en
in pll_en STD_LOGIC
pll enable
Definition: pll_selector.vhd:19

pll_selector.pll_en_3
out pll_en_3 STD_LOGIC
enable pll 3
Definition: pll_selector.vhd:17