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ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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BDTModel_decision_function_22.vhd
1 -- ==============================================================
2 -- Generated by Vitis HLS v2024.1.2
3 -- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
4 -- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
5 -- ==============================================================
6 
7 library IEEE;
8 use IEEE.std_logic_1164.all;
9 use IEEE.numeric_std.all;
10 
11 entity BDTModel_decision_function_22 is
12 port (
13  ap_ready : OUT STD_LOGIC;
14  x_0_val : IN STD_LOGIC_VECTOR (15 downto 0);
15  x_5_val : IN STD_LOGIC_VECTOR (15 downto 0);
16  x_9_val : IN STD_LOGIC_VECTOR (15 downto 0);
17  ap_return : OUT STD_LOGIC_VECTOR (5 downto 0) );
18 end;
19 
20 
21 architecture behav of BDTModel_decision_function_22 is
22  constant ap_const_logic_1 : STD_LOGIC := '1';
23  constant ap_const_boolean_1 : BOOLEAN := true;
24  constant ap_const_lv16_17 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000010111";
25  constant ap_const_lv16_342 : STD_LOGIC_VECTOR (15 downto 0) := "0000001101000010";
26  constant ap_const_lv16_41 : STD_LOGIC_VECTOR (15 downto 0) := "0000000001000001";
27  constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
28  constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
29  constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
30  constant ap_const_lv6_2D : STD_LOGIC_VECTOR (5 downto 0) := "101101";
31  constant ap_const_lv6_33 : STD_LOGIC_VECTOR (5 downto 0) := "110011";
32  constant ap_const_lv6_2E : STD_LOGIC_VECTOR (5 downto 0) := "101110";
33  constant ap_const_lv6_23 : STD_LOGIC_VECTOR (5 downto 0) := "100011";
34  constant ap_const_logic_0 : STD_LOGIC := '0';
35 
36 attribute shreg_extract : string;
37  signal comparison_fu_62_p2 : STD_LOGIC_VECTOR (0 downto 0);
38  signal comparison_30_fu_68_p2 : STD_LOGIC_VECTOR (0 downto 0);
39  signal comparison_31_fu_74_p2 : STD_LOGIC_VECTOR (0 downto 0);
40  signal activation_59_fu_80_p2 : STD_LOGIC_VECTOR (0 downto 0);
41  signal activation_fu_86_p2 : STD_LOGIC_VECTOR (0 downto 0);
42  signal xor_ln170_fu_98_p2 : STD_LOGIC_VECTOR (0 downto 0);
43  signal activation_62_fu_92_p2 : STD_LOGIC_VECTOR (0 downto 0);
44  signal zext_ln170_fu_104_p1 : STD_LOGIC_VECTOR (1 downto 0);
45  signal or_ln170_fu_108_p2 : STD_LOGIC_VECTOR (0 downto 0);
46  signal select_ln170_fu_114_p3 : STD_LOGIC_VECTOR (1 downto 0);
47  signal agg_result_fu_130_p9 : STD_LOGIC_VECTOR (5 downto 0);
48  signal agg_result_fu_130_p10 : STD_LOGIC_VECTOR (1 downto 0);
49  signal agg_result_fu_130_p11 : STD_LOGIC_VECTOR (5 downto 0);
50  signal agg_result_fu_130_p1 : STD_LOGIC_VECTOR (1 downto 0);
51  signal agg_result_fu_130_p3 : STD_LOGIC_VECTOR (1 downto 0);
52  signal agg_result_fu_130_p5 : STD_LOGIC_VECTOR (1 downto 0);
53  signal agg_result_fu_130_p7 : STD_LOGIC_VECTOR (1 downto 0);
54  signal ap_ce_reg : STD_LOGIC;
55 
56  component BDTModel_sparsemux_9_2_6_1_1 IS
57  generic (
58  ID : INTEGER;
59  NUM_STAGE : INTEGER;
60  CASE0 : STD_LOGIC_VECTOR (1 downto 0);
61  din0_WIDTH : INTEGER;
62  CASE1 : STD_LOGIC_VECTOR (1 downto 0);
63  din1_WIDTH : INTEGER;
64  CASE2 : STD_LOGIC_VECTOR (1 downto 0);
65  din2_WIDTH : INTEGER;
66  CASE3 : STD_LOGIC_VECTOR (1 downto 0);
67  din3_WIDTH : INTEGER;
68  def_WIDTH : INTEGER;
69  sel_WIDTH : INTEGER;
70  dout_WIDTH : INTEGER );
71  port (
72  din0 : IN STD_LOGIC_VECTOR (5 downto 0);
73  din1 : IN STD_LOGIC_VECTOR (5 downto 0);
74  din2 : IN STD_LOGIC_VECTOR (5 downto 0);
75  din3 : IN STD_LOGIC_VECTOR (5 downto 0);
76  def : IN STD_LOGIC_VECTOR (5 downto 0);
77  sel : IN STD_LOGIC_VECTOR (1 downto 0);
78  dout : OUT STD_LOGIC_VECTOR (5 downto 0) );
79  end component;
80 
81 
82 
83 begin
84  sparsemux_9_2_6_1_1_U64 : component BDTModel_sparsemux_9_2_6_1_1
85  generic map (
86  ID => 1,
87  NUM_STAGE => 1,
88  CASE0 => "00",
89  din0_WIDTH => 6,
90  CASE1 => "01",
91  din1_WIDTH => 6,
92  CASE2 => "10",
93  din2_WIDTH => 6,
94  CASE3 => "11",
95  din3_WIDTH => 6,
96  def_WIDTH => 6,
97  sel_WIDTH => 2,
98  dout_WIDTH => 6)
99  port map (
100  din0 => ap_const_lv6_2D,
101  din1 => ap_const_lv6_33,
102  din2 => ap_const_lv6_2E,
103  din3 => ap_const_lv6_23,
104  def => agg_result_fu_130_p9,
105  sel => agg_result_fu_130_p10,
106  dout => agg_result_fu_130_p11);
107 
108 
109 
110 
111  activation_59_fu_80_p2 <= (comparison_fu_62_p2 xor ap_const_lv1_1);
112  activation_62_fu_92_p2 <= (comparison_31_fu_74_p2 and activation_59_fu_80_p2);
113  activation_fu_86_p2 <= (comparison_fu_62_p2 and comparison_30_fu_68_p2);
114  agg_result_fu_130_p10 <=
115  select_ln170_fu_114_p3 when (or_ln170_fu_108_p2(0) = '1') else
116  ap_const_lv2_3;
117  agg_result_fu_130_p9 <= "XXXXXX";
118  ap_ready <= ap_const_logic_1;
119  ap_return <= agg_result_fu_130_p11;
120  comparison_30_fu_68_p2 <= "1" when (unsigned(x_0_val) < unsigned(ap_const_lv16_342)) else "0";
121  comparison_31_fu_74_p2 <= "1" when (unsigned(x_5_val) < unsigned(ap_const_lv16_41)) else "0";
122  comparison_fu_62_p2 <= "1" when (unsigned(x_9_val) < unsigned(ap_const_lv16_17)) else "0";
123  or_ln170_fu_108_p2 <= (comparison_fu_62_p2 or activation_62_fu_92_p2);
124  select_ln170_fu_114_p3 <=
125  zext_ln170_fu_104_p1 when (comparison_fu_62_p2(0) = '1') else
126  ap_const_lv2_2;
127  xor_ln170_fu_98_p2 <= (ap_const_lv1_1 xor activation_fu_86_p2);
128  zext_ln170_fu_104_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(xor_ln170_fu_98_p2),2));
129 end behav;
BDTModel_decision_function_22.behav
Definition: BDTModel_decision_function_22.vhd:21
BDTModel_decision_function_22
Definition: BDTModel_decision_function_22.vhd:11
BDTModel_sparsemux_9_2_6_1_1
Definition: BDTModel_sparsemux_9_2_6_1_1.vhd:12
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