BDTModel_decision_function_7.vhd

-- ==============================================================
-- Generated by Vitis HLS v2024.1.2
-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
-- Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
-- ==============================================================
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity BDTModel_decision_function_7 is
port (
    ap_ready : OUT STD_LOGIC;
    x_2_val : IN STD_LOGIC_VECTOR (15 downto 0);
    x_3_val : IN STD_LOGIC_VECTOR (15 downto 0);
    x_6_val : IN STD_LOGIC_VECTOR (15 downto 0);
    ap_return : OUT STD_LOGIC_VECTOR (5 downto 0) );
end;
 
 
architecture behav of BDTModel_decision_function_7 is 
    constant ap_const_logic_1 : STD_LOGIC := '1';
    constant ap_const_boolean_1 : BOOLEAN := true;
    constant ap_const_lv16_2B : STD_LOGIC_VECTOR (15 downto 0) := "0000000000101011";
    constant ap_const_lv16_3C : STD_LOGIC_VECTOR (15 downto 0) := "0000000000111100";
    constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
    constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
    constant ap_const_lv13_0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000000";
    constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
    constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
    constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
    constant ap_const_lv6_2D : STD_LOGIC_VECTOR (5 downto 0) := "101101";
    constant ap_const_lv6_33 : STD_LOGIC_VECTOR (5 downto 0) := "110011";
    constant ap_const_lv6_2A : STD_LOGIC_VECTOR (5 downto 0) := "101010";
    constant ap_const_lv6_2E : STD_LOGIC_VECTOR (5 downto 0) := "101110";
    constant ap_const_logic_0 : STD_LOGIC := '0';
 
attribute shreg_extract : string;
    signal tmp_fu_80_p4 : STD_LOGIC_VECTOR (12 downto 0);
    signal comparison_fu_68_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal comparison_5_fu_74_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal comparison_6_fu_90_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal activation_9_fu_96_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal activation_fu_102_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal xor_ln170_fu_114_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal activation_12_fu_108_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal zext_ln170_fu_120_p1 : STD_LOGIC_VECTOR (1 downto 0);
    signal or_ln170_fu_124_p2 : STD_LOGIC_VECTOR (0 downto 0);
    signal select_ln170_fu_130_p3 : STD_LOGIC_VECTOR (1 downto 0);
    signal agg_result_fu_146_p9 : STD_LOGIC_VECTOR (5 downto 0);
    signal agg_result_fu_146_p10 : STD_LOGIC_VECTOR (1 downto 0);
    signal agg_result_fu_146_p11 : STD_LOGIC_VECTOR (5 downto 0);
    signal agg_result_fu_146_p1 : STD_LOGIC_VECTOR (1 downto 0);
    signal agg_result_fu_146_p3 : STD_LOGIC_VECTOR (1 downto 0);
    signal agg_result_fu_146_p5 : STD_LOGIC_VECTOR (1 downto 0);
    signal agg_result_fu_146_p7 : STD_LOGIC_VECTOR (1 downto 0);
    signal ap_ce_reg : STD_LOGIC;
 
    component BDTModel_sparsemux_9_2_6_1_1 IS
    generic (
        ID : INTEGER;
        NUM_STAGE : INTEGER;
        CASE0 : STD_LOGIC_VECTOR (1 downto 0);
        din0_WIDTH : INTEGER;
        CASE1 : STD_LOGIC_VECTOR (1 downto 0);
        din1_WIDTH : INTEGER;
        CASE2 : STD_LOGIC_VECTOR (1 downto 0);
        din2_WIDTH : INTEGER;
        CASE3 : STD_LOGIC_VECTOR (1 downto 0);
        din3_WIDTH : INTEGER;
        def_WIDTH : INTEGER;
        sel_WIDTH : INTEGER;
        dout_WIDTH : INTEGER );
    port (
        din0 : IN STD_LOGIC_VECTOR (5 downto 0);
        din1 : IN STD_LOGIC_VECTOR (5 downto 0);
        din2 : IN STD_LOGIC_VECTOR (5 downto 0);
        din3 : IN STD_LOGIC_VECTOR (5 downto 0);
        def : IN STD_LOGIC_VECTOR (5 downto 0);
        sel : IN STD_LOGIC_VECTOR (1 downto 0);
        dout : OUT STD_LOGIC_VECTOR (5 downto 0) );
    end component;
 
 
 
begin
    sparsemux_9_2_6_1_1_U112 : component BDTModel_sparsemux_9_2_6_1_1
    generic map (
        ID => 1,
        NUM_STAGE => 1,
        CASE0 => "00",
        din0_WIDTH => 6,
        CASE1 => "01",
        din1_WIDTH => 6,
        CASE2 => "10",
        din2_WIDTH => 6,
        CASE3 => "11",
        din3_WIDTH => 6,
        def_WIDTH => 6,
        sel_WIDTH => 2,
        dout_WIDTH => 6)
    port map (
        din0 => ap_const_lv6_2D,
        din1 => ap_const_lv6_33,
        din2 => ap_const_lv6_2A,
        din3 => ap_const_lv6_2E,
        def => agg_result_fu_146_p9,
        sel => agg_result_fu_146_p10,
        dout => agg_result_fu_146_p11);
 
 
 
 
    activation_12_fu_108_p2 <= (comparison_6_fu_90_p2 and activation_9_fu_96_p2);
    activation_9_fu_96_p2 <= (comparison_fu_68_p2 xor ap_const_lv1_1);
    activation_fu_102_p2 <= (comparison_fu_68_p2 and comparison_5_fu_74_p2);
    agg_result_fu_146_p10 <= 
        select_ln170_fu_130_p3 when (or_ln170_fu_124_p2(0) = '1') else 
        ap_const_lv2_3;
    agg_result_fu_146_p9 <= "XXXXXX";
    ap_ready <= ap_const_logic_1;
    ap_return <= agg_result_fu_146_p11;
    comparison_5_fu_74_p2 <= "1" when (unsigned(x_6_val) < unsigned(ap_const_lv16_3C)) else "0";
    comparison_6_fu_90_p2 <= "1" when (tmp_fu_80_p4 = ap_const_lv13_0) else "0";
    comparison_fu_68_p2 <= "1" when (unsigned(x_2_val) < unsigned(ap_const_lv16_2B)) else "0";
    or_ln170_fu_124_p2 <= (comparison_fu_68_p2 or activation_12_fu_108_p2);
    select_ln170_fu_130_p3 <= 
        zext_ln170_fu_120_p1 when (comparison_fu_68_p2(0) = '1') else 
        ap_const_lv2_2;
    tmp_fu_80_p4 <= x_3_val(15 downto 3);
    xor_ln170_fu_114_p2 <= (ap_const_lv1_1 xor activation_fu_102_p2);
    zext_ln170_fu_120_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(xor_ln170_fu_114_p2),2));
end behav;