LoadGenerator.vhd File Reference

Load generator. More...

Go to the source code of this file.

Entities
LoadGenerator	entity
	Load generator. More...
Behavioral	architecture
	Load generator. More...

Detailed Description

Load generator.

This module generates a load signal for algorithm data. It is derived from the load clock, having a 40 MHz frequency a 12% duty cycle (shorter than 200MHz and 280MHz. The OUT_Load200 and 280 signals are synchronised with the 200 and 280 MHz clock The two phases should be set according to the simulation and to the multicycle constraints: 40 to 200 and 200 to 280

Author

Francesco Gonnella

Definition in file LoadGenerator.vhd.