BDTModel Entity Reference

Inheritance diagram for BDTModel:

Entities
behav	architecture

Libraries
IEEE

Use Clauses
std_logic_1164
numeric_std

Ports
ap_clk	in	STD_LOGIC
x_0	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_1	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_2	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_3	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_4	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_5	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_6	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_7	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_8	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_9	in	STD_LOGIC_VECTOR ( 15 downto 0 )
x_10	in	STD_LOGIC_VECTOR ( 15 downto 0 )
score_0	out	STD_LOGIC_VECTOR ( 10 downto 0 )
score_0_ap_vld	out	STD_LOGIC

Detailed Description

Definition at line 11 of file BDTModel.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/TauBDT/HLS/BDTModel.vhd