eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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Attributes | Components | Constants | Instantiations | Signals
behav Architecture Reference

Components

BDTModel_sparsemux_9_2_6_1_1  <Entity BDTModel_sparsemux_9_2_6_1_1>

Constants

ap_const_logic_1  STD_LOGIC := ' 1 '
ap_const_boolean_1  BOOLEAN := true
ap_const_lv16_1F7  STD_LOGIC_VECTOR ( 15 downto 0 ) := " 0000000111110111 "
ap_const_lv32_3  STD_LOGIC_VECTOR ( 31 downto 0 ) := " 00000000000000000000000000000011 "
ap_const_lv32_F  STD_LOGIC_VECTOR ( 31 downto 0 ) := " 00000000000000000000000000001111 "
ap_const_lv13_0  STD_LOGIC_VECTOR ( 12 downto 0 ) := " 0000000000000 "
ap_const_lv16_D  STD_LOGIC_VECTOR ( 15 downto 0 ) := " 0000000000001101 "
ap_const_lv1_1  STD_LOGIC_VECTOR ( 0 downto 0 ) := " 1 "
ap_const_lv2_2  STD_LOGIC_VECTOR ( 1 downto 0 ) := " 10 "
ap_const_lv2_3  STD_LOGIC_VECTOR ( 1 downto 0 ) := " 11 "
ap_const_lv6_27  STD_LOGIC_VECTOR ( 5 downto 0 ) := " 100111 "
ap_const_lv6_2E  STD_LOGIC_VECTOR ( 5 downto 0 ) := " 101110 "
ap_const_lv6_35  STD_LOGIC_VECTOR ( 5 downto 0 ) := " 110101 "
ap_const_lv6_21  STD_LOGIC_VECTOR ( 5 downto 0 ) := " 100001 "
ap_const_logic_0  STD_LOGIC := ' 0 '

Signals

tmp_fu_74_p4  STD_LOGIC_VECTOR ( 12 downto 0 )
comparison_fu_68_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
comparison_9_fu_84_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
comparison_10_fu_90_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
activation_17_fu_96_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
activation_fu_102_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
xor_ln170_fu_114_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
activation_20_fu_108_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
zext_ln170_fu_120_p1  STD_LOGIC_VECTOR ( 1 downto 0 )
or_ln170_fu_124_p2  STD_LOGIC_VECTOR ( 0 downto 0 )
select_ln170_fu_130_p3  STD_LOGIC_VECTOR ( 1 downto 0 )
agg_result_fu_146_p9  STD_LOGIC_VECTOR ( 5 downto 0 )
agg_result_fu_146_p10  STD_LOGIC_VECTOR ( 1 downto 0 )
agg_result_fu_146_p11  STD_LOGIC_VECTOR ( 5 downto 0 )
agg_result_fu_146_p1  STD_LOGIC_VECTOR ( 1 downto 0 )
agg_result_fu_146_p3  STD_LOGIC_VECTOR ( 1 downto 0 )
agg_result_fu_146_p5  STD_LOGIC_VECTOR ( 1 downto 0 )
agg_result_fu_146_p7  STD_LOGIC_VECTOR ( 1 downto 0 )
ap_ce_reg  STD_LOGIC

Attributes

shreg_extract  string

Instantiations

sparsemux_9_2_6_1_1_u17  BDTModel_sparsemux_9_2_6_1_1 <Entity BDTModel_sparsemux_9_2_6_1_1>

Detailed Description

Definition at line 21 of file BDTModel_decision_function_5.vhd.


The documentation for this class was generated from the following file: