rtl Architecture Reference

Functions
std_logic_vector	ToIndirectInitVal ( Direct: in std_logic_vector CRC_Width: in positive Poly: in std_logic_vector )

Processes
PROCESS_40	( Clk )

Constants
Poly	Std_Logic_Vector ( CRC_Width- 1 downto 0 ) := G_Poly
InitVal	Std_Logic_Vector ( CRC_Width- 1 downto 0 ) := G_InitVal
InDirectInitVal	std_logic_vector ( CRC_Width- 1 downto 0 ) := ToIndirectInitVal ( InitVal , CRC_Width , Poly )

Signals
Reg_s	std_logic_vector ( CRC_Width- 1 downto 0 )

Detailed Description

Definition at line 31 of file crc-20.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/crc-20.vhd