FastFifo Entity Reference

Fast FIFO, without control signal but with 1 clock tick i/0 delay. More...

Inheritance diagram for FastFifo:

Entities
str	architecture
	Fast FIFO, without control signal but with 1 clock tick i/0 delay. More...

Libraries
ieee
algolib

Use Clauses
std_logic_1164
numeric_std
DataTypes	Package <DataTypes>
AlgoDataTypes	Package <AlgoDataTypes>

Generics
FASTFIFO_DATA_DEPTH	integer := 8
FASTFIFO_ADDRESS_DEPTH	integer := 3

Ports
clk	in	std_logic
IN_Reset	in	std_logic
IN_Data	in	AlgoTriggerObject
IN_Write	in	std_logic
IN_Ack	in	std_logic
OUT_Empty	out	std_logic
OUT_Data	out	AlgoTriggerObject

Detailed Description

Fast FIFO, without control signal but with 1 clock tick i/0 delay.

LastWrite (read) should be set to 1 while writing(reading) the last word It will reset the writing (reading) address at the next clock cycle

Author

Francesco Gonnella

Definition at line 18 of file FastFifo.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/FastFifo.vhd