str Architecture Reference

Fast FIFO, without control signal but with 1 clock tick i/0 delay. More...

Processes
reading	( clk )
writing	( clk )
memory	( clk )

Signals
mem	AlgoTriggerObjects ( FASTFIFO_DATA_DEPTH- 1 downto 0 ) := ( others = > ZERO_ALGO_TRIGGER_OBJECT )
ReadAddress	std_logic_vector ( FASTFIFO_ADDRESS_DEPTH- 1 downto 0 ) := ( others = > ' 0 ' )
WriteAddress	std_logic_vector ( FASTFIFO_ADDRESS_DEPTH- 1 downto 0 ) := ( others = > ' 0 ' )
Address	std_logic_vector ( FASTFIFO_ADDRESS_DEPTH- 1 downto 0 ) := ( others = > ' 0 ' )
Empty	std_logic

Detailed Description

Fast FIFO, without control signal but with 1 clock tick i/0 delay.

LastWrite (read) should be set to 1 while writing(reading) the last word It will reset the writing (reading) address at the next clock cycle

Author

Francesco Gonnella

Definition at line 39 of file FastFifo.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/FastFifo.vhd