Behavioral Architecture Reference

Calorimeter data PISO for process FPGA. More...

Processes
U2_280M_clk	( CLK_280M_i )
U3_wr_to_DPR_fsm	( CLK_280M_i )

Types
STATE_TYPE	( idle , ser_1 , ser_2 , ser_3 , ser_4 , ser_5 , ser_6 , ser_7 )

Signals
CLK_280M_i	std_logic
RST_i	std_logic
data_sync_in_1	std_logic
data_sync_in_2	std_logic
RAW_data_in_i	STD_LOGIC_VECTOR ( 223 downto 0 ) := ( others = > ' 0 ' )
data_sync_out_i	std_logic
data_out_valid_i	std_logic
data_out_i	STD_LOGIC_VECTOR ( 35 downto 0 )
error_flag_i	STD_LOGIC_VECTOR ( 3 downto 0 )
current_state	STATE_TYPE

Attributes
keep	string
max_fanout	integer
keep	signal is " true "
max_fanout	signal is 30

Detailed Description

Calorimeter data PISO for process FPGA.

This is module takes the calorimeter data in at 224 bits per MGT channel, then generates 7 x 32-bit data together with 7 x 1b valid and 1b synch signals

It also changes the 32-b input data to 36-bit ouput data by adding the 4-bit error flags to the 36-bit word. The 4 bit error flags are used when constructing an RAW Readout Frame (event) which are: zero + input_crc + input_disparity + not_in_table

Author

Saeed Taghavi

Definition at line 42 of file PISO_RAW_data.vhd.

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The documentation for this class was generated from the following file:

• Readout/src/PISO_RAW_data.vhd