SRL16E_35 Entity Reference

shift register More...

Inheritance diagram for SRL16E_35:

Entities
Behavioral	architecture
	shift register More...

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
std_logic_arith
vcomponents

Ports
clk	in	std_logic
		clock
srl_en	in	std_logic
		enable of shifter
address	in	std_logic_vector ( 3 downto 0 )
		shift depth
data_in	in	std_logic_vector ( 36 downto 0 )
		data in
data_out	out	std_logic_vector ( 36 downto 0 )
		data out

Detailed Description

shift register

Shift register that use xilinx SRL16E It can shift up to 4-bit shift depth and can be select through ipbus

Author

Mohammed Siyad

Definition at line 14 of file srl16e_35.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/srl16e_35.vhd