Behavioral Architecture Reference

shift register More...

Signals
d_i	std_logic_vector ( 36 downto 0 )
q_i	std_logic_vector ( 36 downto 0 )

Instantiations
srl16e_inst_36	srl16e

Detailed Description

shift register

Shift register that use xilinx SRL16E It can shift up to 4-bit shift depth and can be select through ipbus

Author

Mohammed Siyad

Definition at line 31 of file srl16e_35.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/Data_Path/srl16e_35.vhd