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eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
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Back to eFEX documentation
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eFEX firmware
1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards
|
Top feature-extracting algorithm module. More...
Processes | |
| COUNTERS | ( clk200 ) |
| OUTPUT_SIGNALS_PROCESS | ( clk200 ) |
Signals | |
| OutEgTOB | TriggerObjects_eg ( OUTPUT_TOBS- 1 downto 0 ) |
| OutTauTOB | TriggerObjects_tau ( OUTPUT_TOBS- 1 downto 0 ) |
| SR_InData | TriggerTowerMatrix |
| SR_Load | std_logic |
| SR_LeftRight | std_logic |
| SR_Edge | std_logic |
| SR_OutData | TriggerTowers ( 29 downto 0 ) |
| eg_ParWs | AlgoParameters ( 2 downto 0 ) |
| eg_ParReta | AlgoParameters ( 2 downto 0 ) |
| eg_ParHadron | AlgoParameters ( 2 downto 0 ) |
| eg_Control | AlgoRegister |
| eg_Status | AlgoRegister |
| eg_Data | TriggerTowersArray ( 7 downto 0 ) ( 8 downto 0 ) |
| eg_TOB | TriggerObjects_eg ( 7 downto 0 ) |
| tau_ParJet | AlgoParameters ( 2 downto 0 ) |
| tau_ParFrac | AlgoParameters ( 2 downto 0 ) |
| tau_Control | AlgoRegister |
| tau_Status | AlgoRegister |
| tau_Data | TriggerTowersArray ( 7 downto 0 ) ( 8 downto 0 ) |
| tau_TOB | TriggerObjects_tau ( 7 downto 0 ) |
| RAMCounter | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
| InputCounter | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
| OutputCounter | std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' ) |
| OutputValid | std_logic |
Attributes | |
| keep | string |
| max_fanout | integer |
| keep | signal is " true " |
| max_fanout | signal is 80 |
Instantiations | |
| data_shift_register | AlgoShiftRegister <Entity AlgoShiftRegister> |
| aglo_core_eg | AlgoCore_eg <Entity AlgoCore_eg> |
| aglo_core_tau_bdt | AlgoCore_tau_bdt <Entity AlgoCore_tau_bdt> |
| aglo_core_tau | AlgoCore_tau <Entity AlgoCore_tau> |
Top feature-extracting algorithm module.
The output TOBS are sent in 5 clock cycles. Only eFEX handlig edge region really need to send out 5 TOBs per BC, most of the mouldes just need to send 4 TOBs. This is handled by the input position register. If bit 1 is '1', then theeFEX is an edge module, in this case bit 0 specifies whether the efex is at the left edge (low eta) bit 0 = '0' or at right edge (high eta) bit 0 = '1'. Bit 0 is otherwise ignored.
Definition at line 91 of file TopAlgoModule.vhd.
1.9.1