ctrl_synch_latch Entity Reference

latch enable for the control FPGA More...

Entities
Behavioral	architecture
	latch enable for the control FPGA More...

Libraries
IEEE
xil_defaultlib

Use Clauses
STD_LOGIC_1164
std_logic_arith

Ports
CLK160	in	std_logic
		rx clock
MGT_COMMADET	in	std_logic
		mgt commadet
latch_enable	out	std_logic
		latch enable

Detailed Description

latch enable for the control FPGA

It generates latch enable pulse in every 4 clocks of rx clock

Author

Mohammed Siyad

Definition at line 14 of file ctrl_synch_latch.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/ctrl_synch_latch.vhd