Behavioral Architecture Reference

latch enable for the control FPGA More...

Processes
PROCESS_41	( clk160 )

Signals
cntr	unsigned ( 3 downto 0 ) := " 0000 "

Detailed Description

latch enable for the control FPGA

It generates latch enable pulse in every 4 clocks of rx clock

Author

Mohammed Siyad

Definition at line 26 of file ctrl_synch_latch.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/data_path/ctrl_synch_latch.vhd