implementation Architecture Reference

Processes
REG_P_IN	( prmry_aclk )
P_IN_CROSS2SCNDRY	( scndry_aclk )
REG_PLEVEL_IN	( prmry_aclk )
CROSS_PLEVEL_IN2SCNDRY	( scndry_aclk )
CROSS_PLEVEL_IN2SCNDRY	( scndry_aclk )
REG_PLEVEL_IN	( prmry_aclk )
CROSS_PLEVEL_IN2SCNDRY	( scndry_aclk )
CROSS_PLEVEL_SCNDRY2PRMRY	( prmry_aclk )

Signals
s_out_d1_efex_aurora_hub2_cdc_to	std_logic := ' 0 '
s_out_d2	std_logic := ' 0 '
s_out_d3	std_logic := ' 0 '
s_out_d4	std_logic := ' 0 '
s_out_d5	std_logic := ' 0 '
s_out_d6	std_logic := ' 0 '
s_out_d7	std_logic := ' 0 '
s_out_re	std_logic := ' 0 '
prmry_in_xored	std_logic := ' 0 '
p_in_d1_cdc_from	std_logic := ' 0 '
p_level_in_d1_cdc_from	std_logic := ' 0 '
p_level_in_int	std_logic := ' 0 '
s_level_out_d1_efex_aurora_hub2_cdc_to	std_logic := ' 0 '
s_level_out_d2	std_logic := ' 0 '
s_level_out_d3	std_logic := ' 0 '
s_level_out_d4	std_logic := ' 0 '
s_level_out_d5	std_logic := ' 0 '
s_level_out_d6	std_logic := ' 0 '
p_level_in_bus_d1_cdc_from	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
s_level_out_bus_d1_efex_aurora_hub2_cdc_to	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
s_level_out_bus_d1_cdc_tig	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
s_level_out_bus_d2	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
s_level_out_bus_d3	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
s_level_out_bus_d4	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
s_level_out_bus_d5	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
s_level_out_bus_d6	std_logic_vector ( C_VECTOR_WIDTH- 1 downto 0 )
p_level_out_d1_efex_aurora_hub2_cdc_to	std_logic := ' 0 '
p_level_out_d2	std_logic := ' 0 '
p_level_out_d3	std_logic := ' 0 '
p_level_out_d4	std_logic := ' 0 '
p_level_out_d5	std_logic := ' 0 '
p_level_out_d6	std_logic := ' 0 '
p_level_out_d7	std_logic := ' 0 '
scndry_out_int	std_logic := ' 0 '
prmry_pulse_ack	std_logic := ' 0 '

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	architecture is " yes "
async_reg	STRING
async_reg	signal is " true "
shift_extract	STRING
shift_extract	signal is " no "
keep	STRING
keep	signal is " true "

Detailed Description

Definition at line 153 of file efex_aurora_hub2_cdc_sync_exdes.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_cdc_sync_exdes.vhd