efex_aurora_hub2_support Entity Reference

Inheritance diagram for efex_aurora_hub2_support:

Entities
STRUCTURE	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
std_logic_misc
numeric_std
std_logic_arith
std_logic_unsigned
VCOMPONENTS

Ports
s_axi_tx_tdata	in	std_logic_vector ( 63 downto 0 )
s_axi_tx_tkeep	in	std_logic_vector ( 7 downto 0 )
s_axi_tx_tvalid	in	std_logic
s_axi_tx_tready	out	std_logic
s_axi_tx_tlast	in	std_logic
s_axi_ufc_tx_req	in	std_logic
s_axi_ufc_tx_ms	in	std_logic_vector ( 2 downto 0 )
s_axi_ufc_tx_ack	out	std_logic
txp	out	std_logic_vector ( 0 to 3 )
txn	out	std_logic_vector ( 0 to 3 )
gt_refclk1_p	in	std_logic
gt_refclk1_n	in	std_logic
tx_hard_err	out	std_logic
tx_lane_up	out	std_logic_vector ( 0 to 3 )
tx_channel_up	out	std_logic
user_clk_out	out	std_logic
tx_system_reset	in	std_logic
gt_reset	in	std_logic
sys_reset_out	out	std_logic
power_down	in	std_logic
loopback	in	std_logic_vector ( 2 downto 0 )
init_clk	in	std_logic
tx_lock	out	std_logic
init_clk_out	out	std_logic
tx_resetdone_out	out	std_logic
gt0_cplllock_out	out	std_logic
gt0_txpostcursor_in	in	std_logic_vector ( 4 downto 0 )
gt0_txprecursor_in	in	std_logic_vector ( 4 downto 0 )
gt0_txchardispmode_in	in	std_logic_vector ( 1 downto 0 )
gt0_txchardispval_in	in	std_logic_vector ( 1 downto 0 )
gt0_txdiffctrl_in	in	std_logic_vector ( 3 downto 0 )
gt0_txmaincursor_in	in	std_logic_vector ( 6 downto 0 )
gt0_txpolarity_in	in	std_logic
gt0_tx_buf_err_out	out	std_logic
gt0_txprbsforceerr_in	in	std_logic
gt0_txprbssel_in	in	std_logic_vector ( 2 downto 0 )
gt0_txpcsreset_in	in	std_logic
gt0_txinhibit_in	in	std_logic
gt0_txpmareset_in	in	std_logic
gt0_txresetdone_out	out	std_logic
gt0_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
gt1_cplllock_out	out	std_logic
gt1_txpostcursor_in	in	std_logic_vector ( 4 downto 0 )
gt1_txprecursor_in	in	std_logic_vector ( 4 downto 0 )
gt1_txchardispmode_in	in	std_logic_vector ( 1 downto 0 )
gt1_txchardispval_in	in	std_logic_vector ( 1 downto 0 )
gt1_txdiffctrl_in	in	std_logic_vector ( 3 downto 0 )
gt1_txmaincursor_in	in	std_logic_vector ( 6 downto 0 )
gt1_txpolarity_in	in	std_logic
gt1_tx_buf_err_out	out	std_logic
gt1_txprbsforceerr_in	in	std_logic
gt1_txprbssel_in	in	std_logic_vector ( 2 downto 0 )
gt1_txpcsreset_in	in	std_logic
gt1_txinhibit_in	in	std_logic
gt1_txpmareset_in	in	std_logic
gt1_txresetdone_out	out	std_logic
gt1_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
gt2_cplllock_out	out	std_logic
gt2_txpostcursor_in	in	std_logic_vector ( 4 downto 0 )
gt2_txprecursor_in	in	std_logic_vector ( 4 downto 0 )
gt2_txchardispmode_in	in	std_logic_vector ( 1 downto 0 )
gt2_txchardispval_in	in	std_logic_vector ( 1 downto 0 )
gt2_txdiffctrl_in	in	std_logic_vector ( 3 downto 0 )
gt2_txmaincursor_in	in	std_logic_vector ( 6 downto 0 )
gt2_txpolarity_in	in	std_logic
gt2_tx_buf_err_out	out	std_logic
gt2_txprbsforceerr_in	in	std_logic
gt2_txprbssel_in	in	std_logic_vector ( 2 downto 0 )
gt2_txpcsreset_in	in	std_logic
gt2_txinhibit_in	in	std_logic
gt2_txpmareset_in	in	std_logic
gt2_txresetdone_out	out	std_logic
gt2_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
gt3_cplllock_out	out	std_logic
gt3_txpostcursor_in	in	std_logic_vector ( 4 downto 0 )
gt3_txprecursor_in	in	std_logic_vector ( 4 downto 0 )
gt3_txchardispmode_in	in	std_logic_vector ( 1 downto 0 )
gt3_txchardispval_in	in	std_logic_vector ( 1 downto 0 )
gt3_txdiffctrl_in	in	std_logic_vector ( 3 downto 0 )
gt3_txmaincursor_in	in	std_logic_vector ( 6 downto 0 )
gt3_txpolarity_in	in	std_logic
gt3_tx_buf_err_out	out	std_logic
gt3_txprbsforceerr_in	in	std_logic
gt3_txprbssel_in	in	std_logic_vector ( 2 downto 0 )
gt3_txpcsreset_in	in	std_logic
gt3_txinhibit_in	in	std_logic
gt3_txpmareset_in	in	std_logic
gt3_txresetdone_out	out	std_logic
gt3_txbufstatus_out	out	std_logic_vector ( 1 downto 0 )
drpclk_in	in	std_logic
drpaddr_in	in	std_logic_vector ( 8 downto 0 )
drpdi_in	in	std_logic_vector ( 15 downto 0 )
drpdo_out	out	std_logic_vector ( 15 downto 0 )
drpen_in	in	std_logic
drprdy_out	out	std_logic
drpwe_in	in	std_logic
drpaddr_in_lane1	in	std_logic_vector ( 8 downto 0 )
drpdi_in_lane1	in	std_logic_vector ( 15 downto 0 )
drpdo_out_lane1	out	std_logic_vector ( 15 downto 0 )
drpen_in_lane1	in	std_logic
drprdy_out_lane1	out	std_logic
drpwe_in_lane1	in	std_logic
drpaddr_in_lane2	in	std_logic_vector ( 8 downto 0 )
drpdi_in_lane2	in	std_logic_vector ( 15 downto 0 )
drpdo_out_lane2	out	std_logic_vector ( 15 downto 0 )
drpen_in_lane2	in	std_logic
drprdy_out_lane2	out	std_logic
drpwe_in_lane2	in	std_logic
drpaddr_in_lane3	in	std_logic_vector ( 8 downto 0 )
drpdi_in_lane3	in	std_logic_vector ( 15 downto 0 )
drpdo_out_lane3	out	std_logic_vector ( 15 downto 0 )
drpen_in_lane3	in	std_logic
drprdy_out_lane3	out	std_logic
drpwe_in_lane3	in	std_logic
pll_not_locked_out	out	std_logic

Detailed Description

Definition at line 61 of file efex_aurora_hub2_support.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_support.vhd