eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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efex_aurora_hub2_support.vhd
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48 ------------------------------------------------------------------------------/
49  library ieee;
50  use ieee.std_logic_1164.all;
51  use ieee.std_logic_misc.all;
52  use IEEE.numeric_std.all;
53  use ieee.std_logic_arith.all;
54  use ieee.std_logic_unsigned.all;
55 
56 -- synthesis translate_off
57 library UNISIM;
58 use UNISIM.VCOMPONENTS.ALL;
59 -- synthesis translate_on
60 
61 entity efex_aurora_hub2_support is
62 port (
63  -- AXI TX Interface
64  s_axi_tx_tdata : in std_logic_vector(63 downto 0);
65  s_axi_tx_tkeep : in std_logic_vector(7 downto 0);
66  s_axi_tx_tvalid : in std_logic;
67  s_axi_tx_tready : out std_logic;
68  s_axi_tx_tlast : in std_logic;
69  -- User Flow Control TX Interface
70  s_axi_ufc_tx_req : in std_logic;
71  s_axi_ufc_tx_ms : in std_logic_vector(2 downto 0);
72  s_axi_ufc_tx_ack : out std_logic;
73  txp : out std_logic_vector(0 to 3);
74  txn : out std_logic_vector(0 to 3);
75  -- GT Reference Clock Interface
76  gt_refclk1_p : in std_logic;
77  gt_refclk1_n : in std_logic;
78  -- Error Detection Interface
79  tx_hard_err : out std_logic;
80  -- Status
81  tx_lane_up : out std_logic_vector(0 to 3);
82  tx_channel_up : out std_logic;
83  -- System Interface
84  user_clk_out : out std_logic;
85  tx_system_reset : in std_logic;
86  gt_reset : in std_logic;
87  sys_reset_out : out std_logic;
88  power_down : in std_logic;
89  loopback : in std_logic_vector(2 downto 0);
90  init_clk : in std_logic;
91  tx_lock : out std_logic;
92  init_clk_out : out std_logic;
93  tx_resetdone_out : out std_logic;
94  gt0_cplllock_out : out std_logic;
95 
96  ------------------------ TX Configurable Driver Ports ----------------------
97  gt0_txpostcursor_in : in std_logic_vector(4 downto 0);
98  gt0_txprecursor_in : in std_logic_vector(4 downto 0);
99  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
100  gt0_txchardispmode_in : in std_logic_vector(1 downto 0);
101  gt0_txchardispval_in : in std_logic_vector(1 downto 0);
102  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
103  gt0_txmaincursor_in : in std_logic_vector(6 downto 0);
104  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
105  gt0_txpolarity_in : in std_logic;
106  gt0_tx_buf_err_out : out std_logic;
107  ------------------ Transmit Ports - Pattern Generator Ports ----------------
108  gt0_txprbsforceerr_in : in std_logic;
109  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
110  ------------------- Transmit Ports - TX Data Path interface -----------------
111  gt0_txpcsreset_in : in std_logic;
112  gt0_txinhibit_in : in std_logic;
113  gt0_txpmareset_in : in std_logic;
114  gt0_txresetdone_out : out std_logic;
115  gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
116  gt1_cplllock_out : out std_logic;
117 
118 
119  ------------------------ TX Configurable Driver Ports ----------------------
120  gt1_txpostcursor_in : in std_logic_vector(4 downto 0);
121  gt1_txprecursor_in : in std_logic_vector(4 downto 0);
122  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
123  gt1_txchardispmode_in : in std_logic_vector(1 downto 0);
124  gt1_txchardispval_in : in std_logic_vector(1 downto 0);
125  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
126  gt1_txmaincursor_in : in std_logic_vector(6 downto 0);
127  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
128  gt1_txpolarity_in : in std_logic;
129  gt1_tx_buf_err_out : out std_logic;
130  ------------------ Transmit Ports - Pattern Generator Ports ----------------
131  gt1_txprbsforceerr_in : in std_logic;
132  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
133  ------------------- Transmit Ports - TX Data Path interface -----------------
134  gt1_txpcsreset_in : in std_logic;
135  gt1_txinhibit_in : in std_logic;
136  gt1_txpmareset_in : in std_logic;
137  gt1_txresetdone_out : out std_logic;
138  gt1_txbufstatus_out : out std_logic_vector(1 downto 0);
139  gt2_cplllock_out : out std_logic;
140 
141 
142  ------------------------ TX Configurable Driver Ports ----------------------
143  gt2_txpostcursor_in : in std_logic_vector(4 downto 0);
144  gt2_txprecursor_in : in std_logic_vector(4 downto 0);
145  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
146  gt2_txchardispmode_in : in std_logic_vector(1 downto 0);
147  gt2_txchardispval_in : in std_logic_vector(1 downto 0);
148  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
149  gt2_txmaincursor_in : in std_logic_vector(6 downto 0);
150  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
151  gt2_txpolarity_in : in std_logic;
152  gt2_tx_buf_err_out : out std_logic;
153  ------------------ Transmit Ports - Pattern Generator Ports ----------------
154  gt2_txprbsforceerr_in : in std_logic;
155  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
156  ------------------- Transmit Ports - TX Data Path interface -----------------
157  gt2_txpcsreset_in : in std_logic;
158  gt2_txinhibit_in : in std_logic;
159  gt2_txpmareset_in : in std_logic;
160  gt2_txresetdone_out : out std_logic;
161  gt2_txbufstatus_out : out std_logic_vector(1 downto 0);
162  gt3_cplllock_out : out std_logic;
163 
164 
165  ------------------------ TX Configurable Driver Ports ----------------------
166  gt3_txpostcursor_in : in std_logic_vector(4 downto 0);
167  gt3_txprecursor_in : in std_logic_vector(4 downto 0);
168  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
169  gt3_txchardispmode_in : in std_logic_vector(1 downto 0);
170  gt3_txchardispval_in : in std_logic_vector(1 downto 0);
171  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
172  gt3_txmaincursor_in : in std_logic_vector(6 downto 0);
173  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
174  gt3_txpolarity_in : in std_logic;
175  gt3_tx_buf_err_out : out std_logic;
176  ------------------ Transmit Ports - Pattern Generator Ports ----------------
177  gt3_txprbsforceerr_in : in std_logic;
178  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
179  ------------------- Transmit Ports - TX Data Path interface -----------------
180  gt3_txpcsreset_in : in std_logic;
181  gt3_txinhibit_in : in std_logic;
182  gt3_txpmareset_in : in std_logic;
183  gt3_txresetdone_out : out std_logic;
184  gt3_txbufstatus_out : out std_logic_vector(1 downto 0);
185 
186  --DRP Ports
187  drpclk_in : in std_logic;
188  drpaddr_in : in std_logic_vector(8 downto 0);
189  drpdi_in : in std_logic_vector(15 downto 0);
190  drpdo_out : out std_logic_vector(15 downto 0);
191  drpen_in : in std_logic;
192  drprdy_out : out std_logic;
193  drpwe_in : in std_logic;
194  drpaddr_in_lane1 : in std_logic_vector(8 downto 0);
195  drpdi_in_lane1 : in std_logic_vector(15 downto 0);
196  drpdo_out_lane1 : out std_logic_vector(15 downto 0);
197  drpen_in_lane1 : in std_logic;
198  drprdy_out_lane1 : out std_logic;
199  drpwe_in_lane1 : in std_logic;
200  drpaddr_in_lane2 : in std_logic_vector(8 downto 0);
201  drpdi_in_lane2 : in std_logic_vector(15 downto 0);
202  drpdo_out_lane2 : out std_logic_vector(15 downto 0);
203  drpen_in_lane2 : in std_logic;
204  drprdy_out_lane2 : out std_logic;
205  drpwe_in_lane2 : in std_logic;
206  drpaddr_in_lane3 : in std_logic_vector(8 downto 0);
207  drpdi_in_lane3 : in std_logic_vector(15 downto 0);
208  drpdo_out_lane3 : out std_logic_vector(15 downto 0);
209  drpen_in_lane3 : in std_logic;
210  drprdy_out_lane3 : out std_logic;
211  drpwe_in_lane3 : in std_logic;
212 
213 
214  pll_not_locked_out : out std_logic
215 
216  );
217 
218 end efex_aurora_hub2_support;
219 
220 
221 architecture STRUCTURE of efex_aurora_hub2_support is
222  attribute core_generation_info : string;
223  attribute core_generation_info of STRUCTURE : architecture is "efex_aurora_hub2,aurora_8b10b_v11_1_10,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=left,c_gt_clock_1=GTHQ4,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=1,c_gt_loc_18=2,c_gt_loc_19=3,c_gt_loc_2=X,c_gt_loc_20=4,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=64120,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160300,c_simplex=true,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=TX-only_Simplex}";
224 
225  component efex_aurora_hub2
226  port (
227  -- TX Stream Interface
228  S_AXI_TX_TDATA : in std_logic_vector(63 downto 0);
229  S_AXI_TX_TKEEP : in std_logic_vector(7 downto 0);
230  S_AXI_TX_TVALID : in std_logic;
231  S_AXI_TX_TREADY : out std_logic;
232  S_AXI_TX_TLAST : in std_logic;
233  -- User Flow Control TX Interface
234 
235  S_AXI_UFC_TX_TVALID : in std_logic;
236  S_AXI_UFC_TX_TDATA : in std_logic_vector(2 downto 0);
237  S_AXI_UFC_TX_TREADY : out std_logic;
238 
239  TXP : out std_logic_vector(0 to 3);
240  TXN : out std_logic_vector(0 to 3);
241 
242  -- GT Reference Clock Interface
243  gt_refclk1 : in std_logic;
244 
245  -- Error Detection Interface
246  TX_HARD_ERR : out std_logic;
247 
248  -- Status
249  TX_CHANNEL_UP : out std_logic;
250  TX_LANE_UP : out std_logic_vector(0 to 3);
251 
252 
253 
254 
255 
256 
257  -- System Interface
258 
259  USER_CLK : in std_logic;
260  SYNC_CLK : in std_logic;
261  GT_RESET : in std_logic;
262  TX_SYSTEM_RESET : in std_logic;
263  sys_reset_out : out std_logic;
264  POWER_DOWN : in std_logic;
265  LOOPBACK : in std_logic_vector(2 downto 0);
266  TX_OUT_CLK : out std_logic;
267  INIT_CLK_IN : in std_logic;
268  PLL_NOT_LOCKED : in std_logic;
269  TX_RESETDONE_OUT : out std_logic;
270  gt0_cplllock_out : out std_logic;
271 
272 
273  ------------------------ TX Configurable Driver Ports ----------------------
274  gt0_txpostcursor_in : in std_logic_vector(4 downto 0);
275  gt0_txprecursor_in : in std_logic_vector(4 downto 0);
276  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
277  gt0_txchardispmode_in : in std_logic_vector(1 downto 0);
278  gt0_txchardispval_in : in std_logic_vector(1 downto 0);
279  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
280  gt0_txmaincursor_in : in std_logic_vector(6 downto 0);
281  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
282  gt0_txpolarity_in : in std_logic;
283  gt0_tx_buf_err_out : out std_logic;
284  ------------------ Transmit Ports - Pattern Generator Ports ----------------
285  gt0_txprbsforceerr_in : in std_logic;
286  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
287  ------------------- Transmit Ports - TX Data Path interface -----------------
288  gt0_txpcsreset_in : in std_logic;
289  gt0_txinhibit_in : in std_logic;
290  gt0_txpmareset_in : in std_logic;
291  gt0_txresetdone_out : out std_logic;
292  gt0_txbufstatus_out : out std_logic_vector(1 downto 0);
293  gt1_cplllock_out : out std_logic;
294 
295 
296  ------------------------ TX Configurable Driver Ports ----------------------
297  gt1_txpostcursor_in : in std_logic_vector(4 downto 0);
298  gt1_txprecursor_in : in std_logic_vector(4 downto 0);
299  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
300  gt1_txchardispmode_in : in std_logic_vector(1 downto 0);
301  gt1_txchardispval_in : in std_logic_vector(1 downto 0);
302  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
303  gt1_txmaincursor_in : in std_logic_vector(6 downto 0);
304  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
305  gt1_txpolarity_in : in std_logic;
306  gt1_tx_buf_err_out : out std_logic;
307  ------------------ Transmit Ports - Pattern Generator Ports ----------------
308  gt1_txprbsforceerr_in : in std_logic;
309  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
310  ------------------- Transmit Ports - TX Data Path interface -----------------
311  gt1_txpcsreset_in : in std_logic;
312  gt1_txinhibit_in : in std_logic;
313  gt1_txpmareset_in : in std_logic;
314  gt1_txresetdone_out : out std_logic;
315  gt1_txbufstatus_out : out std_logic_vector(1 downto 0);
316  gt2_cplllock_out : out std_logic;
317 
318 
319  ------------------------ TX Configurable Driver Ports ----------------------
320  gt2_txpostcursor_in : in std_logic_vector(4 downto 0);
321  gt2_txprecursor_in : in std_logic_vector(4 downto 0);
322  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
323  gt2_txchardispmode_in : in std_logic_vector(1 downto 0);
324  gt2_txchardispval_in : in std_logic_vector(1 downto 0);
325  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
326  gt2_txmaincursor_in : in std_logic_vector(6 downto 0);
327  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
328  gt2_txpolarity_in : in std_logic;
329  gt2_tx_buf_err_out : out std_logic;
330  ------------------ Transmit Ports - Pattern Generator Ports ----------------
331  gt2_txprbsforceerr_in : in std_logic;
332  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
333  ------------------- Transmit Ports - TX Data Path interface -----------------
334  gt2_txpcsreset_in : in std_logic;
335  gt2_txinhibit_in : in std_logic;
336  gt2_txpmareset_in : in std_logic;
337  gt2_txresetdone_out : out std_logic;
338  gt2_txbufstatus_out : out std_logic_vector(1 downto 0);
339  gt3_cplllock_out : out std_logic;
340 
341 
342  ------------------------ TX Configurable Driver Ports ----------------------
343  gt3_txpostcursor_in : in std_logic_vector(4 downto 0);
344  gt3_txprecursor_in : in std_logic_vector(4 downto 0);
345  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
346  gt3_txchardispmode_in : in std_logic_vector(1 downto 0);
347  gt3_txchardispval_in : in std_logic_vector(1 downto 0);
348  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
349  gt3_txmaincursor_in : in std_logic_vector(6 downto 0);
350  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
351  gt3_txpolarity_in : in std_logic;
352  gt3_tx_buf_err_out : out std_logic;
353  ------------------ Transmit Ports - Pattern Generator Ports ----------------
354  gt3_txprbsforceerr_in : in std_logic;
355  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
356  ------------------- Transmit Ports - TX Data Path interface -----------------
357  gt3_txpcsreset_in : in std_logic;
358  gt3_txinhibit_in : in std_logic;
359  gt3_txpmareset_in : in std_logic;
360  gt3_txresetdone_out : out std_logic;
361  gt3_txbufstatus_out : out std_logic_vector(1 downto 0);
362 
363  drpclk_in : in std_logic;
364  drpaddr_in : in std_logic_vector(8 downto 0);
365  drpdi_in : in std_logic_vector(15 downto 0);
366  drpdo_out : out std_logic_vector(15 downto 0);
367  drpen_in : in std_logic;
368  drprdy_out : out std_logic;
369  drpwe_in : in std_logic;
370  drpaddr_in_lane1 : in std_logic_vector(8 downto 0);
371  drpdi_in_lane1 : in std_logic_vector(15 downto 0);
372  drpdo_out_lane1 : out std_logic_vector(15 downto 0);
373  drpen_in_lane1 : in std_logic;
374  drprdy_out_lane1 : out std_logic;
375  drpwe_in_lane1 : in std_logic;
376  drpaddr_in_lane2 : in std_logic_vector(8 downto 0);
377  drpdi_in_lane2 : in std_logic_vector(15 downto 0);
378  drpdo_out_lane2 : out std_logic_vector(15 downto 0);
379  drpen_in_lane2 : in std_logic;
380  drprdy_out_lane2 : out std_logic;
381  drpwe_in_lane2 : in std_logic;
382  drpaddr_in_lane3 : in std_logic_vector(8 downto 0);
383  drpdi_in_lane3 : in std_logic_vector(15 downto 0);
384  drpdo_out_lane3 : out std_logic_vector(15 downto 0);
385  drpen_in_lane3 : in std_logic;
386  drprdy_out_lane3 : out std_logic;
387  drpwe_in_lane3 : in std_logic;
388 
389 --------------------{
390 --__________COMMON PORTS _______________________________{
391  ------------------------- Common Block - QPLL Ports ------------------------
392  gt0_qplllock_in : in std_logic;
393  gt0_qpllrefclklost_in : in std_logic;
394  gt0_qpllreset_out : out std_logic;
395  gt_qpllclk_quad5_in : in std_logic;
396  gt_qpllrefclk_quad5_in : in std_logic;
397 --____________________________COMMON PORTS _______________________________}
398  TX_LOCK : out std_logic
399  );
400 
401  end component;
402 
403 
404 component efex_aurora_hub2_gt_common_wrapper
405 port
406 (
407 --____________________________COMMON PORTS ,_______________________________{
408  gt_qpllclk_quad5_i : out std_logic;
409  gt_qpllrefclk_quad5_i : out std_logic;
410 --____________________________COMMON PORTS ,_______________________________}
411  ---------------------- Common Block - Ref Clock Ports ---------------------
412  gt0_gtrefclk0_common_in : in std_logic;
413  ------------------------- Common Block - QPLL Ports ------------------------
414  gt0_qplllock_out : out std_logic;
415  gt0_qplllockdetclk_in : in std_logic;
416  gt0_qpllrefclklost_out : out std_logic;
417  gt0_qpllreset_in : in std_logic
418 
419 );
420 end component;
421 
422 
423  component IBUFDS_GTE2
424  port (
425  O : out std_ulogic;
426  ODIV2 : out std_ulogic;
427  CEB : in std_ulogic;
428  I : in std_ulogic;
429  IB : in std_ulogic
430  );
431  end component;
432 
433  component BUFG
434 
435  port (
436 
437  O : out std_ulogic;
438  I : in std_ulogic
439 
440  );
441 
442  end component;
443 
444  component efex_aurora_hub2_CLOCK_MODULE
445  port (
446  -- INIT_CLK_P : in std_logic;
447  -- INIT_CLK_N : in std_logic;
448  INIT_CLK : in std_logic;
449  INIT_CLK_O : out std_logic;
450  GT_CLK : in std_logic;
451  GT_CLK_LOCKED : in std_logic;
452  USER_CLK : out std_logic;
453  SYNC_CLK : out std_logic;
454  PLL_NOT_LOCKED : out std_logic
455  );
456  end component;
457 
458  component efex_aurora_hub2_SUPPORT_RESET_LOGIC
459  port (
460  RESET : in std_logic;
461  USER_CLK : in std_logic;
462  INIT_CLK_IN : in std_logic;
463  GT_RESET_IN : in std_logic;
464  SYSTEM_RESET : out std_logic;
465  GT_RESET_OUT : out std_logic
466  );
467  end component;
468 
469  component efex_aurora_hub2_cdc_sync is
470  generic (
471  C_CDC_TYPE : integer range 0 to 2 := 1 ;
472  -- 0 is pulse synch
473  -- 1 is level synch
474  -- 2 is ack based level sync
475  C_RESET_STATE : integer range 0 to 1 := 0 ;
476  -- 0 is reset not needed
477  -- 1 is reset needed
478  C_SINGLE_BIT : integer range 0 to 1 := 1 ;
479  -- 0 is bus input
480  -- 1 is single bit input
481  C_FLOP_INPUT : integer range 0 to 1 := 0 ;
482  C_VECTOR_WIDTH : integer range 0 to 32 := 32 ;
483  C_MTBF_STAGES : integer range 0 to 6 := 2
484  -- Vector Data witdth
485  );
486 
487  port (
488  prmry_aclk : in std_logic ; --
489  prmry_resetn : in std_logic ; --
490  prmry_in : in std_logic ; --
491  prmry_vect_in : in std_logic_vector --
492  (C_VECTOR_WIDTH - 1 downto 0) ; --
493  prmry_ack : out std_logic ;
494  --
495  scndry_aclk : in std_logic ; --
496  scndry_resetn : in std_logic ; --
497  --
498  -- Primary to Secondary Clock Crossing --
499  scndry_out : out std_logic ; --
500  --
501  scndry_vect_out : out std_logic_vector --
502  (C_VECTOR_WIDTH - 1 downto 0) --
503 
504  );
505  end component;
506 
507 ------------ Wire declarations
508 --------------------{
509  ------------------------- Common Block - QPLL Ports ------------------------
510 signal gt0_qplllock_i : std_logic;
511 signal gt0_qpllrefclklost_i : std_logic;
512 signal gt0_qpllreset_i : std_logic;
513 signal gt_qpllclk_quad5_i : std_logic;
514 signal gt_qpllrefclk_quad5_i : std_logic;
515 --------------------}
516 signal gt_refclk1 : std_logic;
517 
518 signal tx_out_clk_i : std_logic;
519 signal user_clk_i : std_logic;
520 signal sync_clk_i : std_logic;
521 signal pll_not_locked_i : std_logic;
522 signal tx_lock_i : std_logic;
523 
524 signal init_clk_i : std_logic;
525 signal tx_resetdone_i : std_logic;
526 signal system_reset_i : std_logic;
527 signal gt_reset_i : std_logic;
528 signal drpclk_i : std_logic;
529 signal reset_sync_user_clk : std_logic;
530 signal gt_reset_sync_init_clk : std_logic;
531 begin
532 
533  --*********************************Main Body of Code**********************************
534 
535  IBUFDS_GTE2_CLK1 : IBUFDS_GTE2
536  port map (
537  I => gt_refclk1_p,
538  IB => gt_refclk1_n,
539  CEB => '0',
540  O => gt_refclk1,
541  ODIV2 => OPEN);
542 
543 
544  drpclk_i <= drpclk_in;
545 
546  -- Instantiate a clock module for clock division
547 
548  clock_module_i : efex_aurora_hub2_CLOCK_MODULE
549  port map (
550  --INIT_CLK_P => init_clk_p,
551  --INIT_CLK_N => init_clk_n,
552  INIT_CLK => init_clk,
553  INIT_CLK_O => init_clk_i,
554  GT_CLK => tx_out_clk_i,
555  GT_CLK_LOCKED => tx_lock_i,
556  USER_CLK => user_clk_i,
557  SYNC_CLK => sync_clk_i,
558  PLL_NOT_LOCKED => pll_not_locked_i
559  );
560 
561  -- outputs
562  init_clk_out <= init_clk_i;
563  user_clk_out <= user_clk_i;
564  pll_not_locked_out <= pll_not_locked_i;
565  tx_lock <= tx_lock_i;
566  tx_resetdone_out <= tx_resetdone_i;
567 
568 
569  reset_sync_user_clk <= tx_system_reset;
570  gt_reset_sync_init_clk <= gt_reset;
571 
572  support_reset_logic_i : efex_aurora_hub2_SUPPORT_RESET_LOGIC
573  port map (
574  RESET => reset_sync_user_clk,
575  USER_CLK => user_clk_i,
576  INIT_CLK_IN => init_clk_i,
577  GT_RESET_IN => gt_reset_sync_init_clk,
578  SYSTEM_RESET => system_reset_i,
579  GT_RESET_OUT => gt_reset_i
580  );
581 
582 -------- instance of _gt_common_wrapper ---{
583 gt_common_support : efex_aurora_hub2_gt_common_wrapper
584 
585 port map
586 (
587 --____________________________COMMON PORTS ,_______________________________{
588  gt_qpllclk_quad5_i => gt_qpllclk_quad5_i ,
589  gt_qpllrefclk_quad5_i => gt_qpllrefclk_quad5_i ,
590  ---------------------- Common Block - Ref Clock Ports ---------------------
591  gt0_gtrefclk0_common_in => gt_refclk1,
592 
593  ------------------------- Common Block - QPLL Ports ------------------------
594  gt0_qplllock_out => gt0_qplllock_i,
595  gt0_qplllockdetclk_in => init_clk_i,
596  gt0_qpllrefclklost_out => gt0_qpllrefclklost_i ,
597  gt0_qpllreset_in => gt0_qpllreset_i
598 --____________________________COMMON PORTS ,_______________________________}
599 );
600 
601 
602 -------- instance of _gt_common_wrapper ---}
603 
604  efex_aurora_hub2_i : efex_aurora_hub2
605  port map (
606  -- AXI TX Interface
607  s_axi_tx_tdata => s_axi_tx_tdata,
608  s_axi_tx_tkeep => s_axi_tx_tkeep,
609  s_axi_tx_tvalid => s_axi_tx_tvalid,
610  s_axi_tx_tlast => s_axi_tx_tlast,
611  s_axi_tx_tready => s_axi_tx_tready,
612 
613 
614 
615  -- User Flow Control TX Interface
616  s_axi_ufc_tx_tvalid => s_axi_ufc_tx_req,
617  s_axi_ufc_tx_tdata => s_axi_ufc_tx_ms,
618  s_axi_ufc_tx_tready => s_axi_ufc_tx_ack,
619 
620 
621  -- GT Serial I/O
622  txp => txp,
623  txn => txn,
624 
625  -- GT Reference Clock Interface
626  gt_refclk1 => gt_refclk1,
627  -- Error Detection Interface
628 
629  -- Error Detection Interface
630  tx_hard_err => tx_hard_err,
631 
632  -- Status
633  tx_channel_up => tx_channel_up,
634  tx_lane_up => tx_lane_up,
635 
636 
637 
638 
639  -- System Interface
640  user_clk => user_clk_i,
641  sync_clk => sync_clk_i,
642  tx_system_reset => system_reset_i,
643  sys_reset_out => sys_reset_out,
644  power_down => power_down,
645  loopback => loopback,
646  gt_reset => gt_reset_i,
647  tx_lock => tx_lock_i,
648  init_clk_in => init_clk_i,
649  pll_not_locked => pll_not_locked_i,
650  tx_resetdone_out => tx_resetdone_i,
651 
652  gt0_cplllock_out => gt0_cplllock_out,
653 
654 
655  ------------------------ TX Configurable Driver Ports ----------------------
656  gt0_txpostcursor_in => gt0_txpostcursor_in,
657  gt0_txprecursor_in => gt0_txprecursor_in,
658  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
659  gt0_txchardispmode_in => gt0_txchardispmode_in,
660  gt0_txchardispval_in => gt0_txchardispval_in,
661  gt0_txdiffctrl_in => gt0_txdiffctrl_in,
662  gt0_txmaincursor_in => gt0_txmaincursor_in,
663  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
664  gt0_txpolarity_in => gt0_txpolarity_in,
665  gt0_tx_buf_err_out => gt0_tx_buf_err_out,
666  ------------------ Transmit Ports - Pattern Generator Ports ----------------
667  gt0_txprbsforceerr_in => gt0_txprbsforceerr_in,
668  gt0_txprbssel_in => gt0_txprbssel_in,
669  ------------------- Transmit Ports - TX Data Path interface -----------------
670  gt0_txpcsreset_in => gt0_txpcsreset_in,
671  gt0_txinhibit_in => gt0_txinhibit_in,
672  gt0_txpmareset_in => gt0_txpmareset_in,
673  gt0_txresetdone_out => gt0_txresetdone_out,
674  gt0_txbufstatus_out => gt0_txbufstatus_out,
675 
676  gt1_cplllock_out => gt1_cplllock_out,
677 
678 
679  ------------------------ TX Configurable Driver Ports ----------------------
680  gt1_txpostcursor_in => gt1_txpostcursor_in,
681  gt1_txprecursor_in => gt1_txprecursor_in,
682  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
683  gt1_txchardispmode_in => gt1_txchardispmode_in,
684  gt1_txchardispval_in => gt1_txchardispval_in,
685  gt1_txdiffctrl_in => gt1_txdiffctrl_in,
686  gt1_txmaincursor_in => gt1_txmaincursor_in,
687  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
688  gt1_txpolarity_in => gt1_txpolarity_in,
689  gt1_tx_buf_err_out => gt1_tx_buf_err_out,
690  ------------------ Transmit Ports - Pattern Generator Ports ----------------
691  gt1_txprbsforceerr_in => gt1_txprbsforceerr_in,
692  gt1_txprbssel_in => gt1_txprbssel_in,
693  ------------------- Transmit Ports - TX Data Path interface -----------------
694  gt1_txpcsreset_in => gt1_txpcsreset_in,
695  gt1_txinhibit_in => gt1_txinhibit_in,
696  gt1_txpmareset_in => gt1_txpmareset_in,
697  gt1_txresetdone_out => gt1_txresetdone_out,
698  gt1_txbufstatus_out => gt1_txbufstatus_out,
699 
700  gt2_cplllock_out => gt2_cplllock_out,
701 
702 
703  ------------------------ TX Configurable Driver Ports ----------------------
704  gt2_txpostcursor_in => gt2_txpostcursor_in,
705  gt2_txprecursor_in => gt2_txprecursor_in,
706  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
707  gt2_txchardispmode_in => gt2_txchardispmode_in,
708  gt2_txchardispval_in => gt2_txchardispval_in,
709  gt2_txdiffctrl_in => gt2_txdiffctrl_in,
710  gt2_txmaincursor_in => gt2_txmaincursor_in,
711  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
712  gt2_txpolarity_in => gt2_txpolarity_in,
713  gt2_tx_buf_err_out => gt2_tx_buf_err_out,
714  ------------------ Transmit Ports - Pattern Generator Ports ----------------
715  gt2_txprbsforceerr_in => gt2_txprbsforceerr_in,
716  gt2_txprbssel_in => gt2_txprbssel_in,
717  ------------------- Transmit Ports - TX Data Path interface -----------------
718  gt2_txpcsreset_in => gt2_txpcsreset_in,
719  gt2_txinhibit_in => gt2_txinhibit_in,
720  gt2_txpmareset_in => gt2_txpmareset_in,
721  gt2_txresetdone_out => gt2_txresetdone_out,
722  gt2_txbufstatus_out => gt2_txbufstatus_out,
723 
724  gt3_cplllock_out => gt3_cplllock_out,
725 
726 
727  ------------------------ TX Configurable Driver Ports ----------------------
728  gt3_txpostcursor_in => gt3_txpostcursor_in,
729  gt3_txprecursor_in => gt3_txprecursor_in,
730  ------------------ Transmit Ports - TX 8B/10B Encoder Ports ----------------
731  gt3_txchardispmode_in => gt3_txchardispmode_in,
732  gt3_txchardispval_in => gt3_txchardispval_in,
733  gt3_txdiffctrl_in => gt3_txdiffctrl_in,
734  gt3_txmaincursor_in => gt3_txmaincursor_in,
735  ----------------- Transmit Ports - TX Polarity Control Ports ---------------
736  gt3_txpolarity_in => gt3_txpolarity_in,
737  gt3_tx_buf_err_out => gt3_tx_buf_err_out,
738  ------------------ Transmit Ports - Pattern Generator Ports ----------------
739  gt3_txprbsforceerr_in => gt3_txprbsforceerr_in,
740  gt3_txprbssel_in => gt3_txprbssel_in,
741  ------------------- Transmit Ports - TX Data Path interface -----------------
742  gt3_txpcsreset_in => gt3_txpcsreset_in,
743  gt3_txinhibit_in => gt3_txinhibit_in,
744  gt3_txpmareset_in => gt3_txpmareset_in,
745  gt3_txresetdone_out => gt3_txresetdone_out,
746  gt3_txbufstatus_out => gt3_txbufstatus_out,
747 
748 
749  drpclk_in => drpclk_i,
750  drpaddr_in => drpaddr_in,
751  drpen_in => drpen_in,
752  drpdi_in => drpdi_in,
753  drprdy_out => drprdy_out,
754  drpdo_out => drpdo_out,
755  drpwe_in => drpwe_in,
756  drpaddr_in_lane1 => drpaddr_in_lane1,
757  drpen_in_lane1 => drpen_in_lane1,
758  drpdi_in_lane1 => drpdi_in_lane1,
759  drprdy_out_lane1 => drprdy_out_lane1,
760  drpdo_out_lane1 => drpdo_out_lane1,
761  drpwe_in_lane1 => drpwe_in_lane1,
762  drpaddr_in_lane2 => drpaddr_in_lane2,
763  drpen_in_lane2 => drpen_in_lane2,
764  drpdi_in_lane2 => drpdi_in_lane2,
765  drprdy_out_lane2 => drprdy_out_lane2,
766  drpdo_out_lane2 => drpdo_out_lane2,
767  drpwe_in_lane2 => drpwe_in_lane2,
768  drpaddr_in_lane3 => drpaddr_in_lane3,
769  drpen_in_lane3 => drpen_in_lane3,
770  drpdi_in_lane3 => drpdi_in_lane3,
771  drprdy_out_lane3 => drprdy_out_lane3,
772  drpdo_out_lane3 => drpdo_out_lane3,
773  drpwe_in_lane3 => drpwe_in_lane3,
774 --------------------{
775 --__________COMMON PORTS _______________________________{
776  ------------------------- Common Block - QPLL Ports ------------------------
777  gt0_qplllock_in => gt0_qplllock_i,
778  gt0_qpllrefclklost_in => gt0_qpllrefclklost_i,
779  gt0_qpllreset_out => gt0_qpllreset_i,
780  gt_qpllclk_quad5_in => gt_qpllclk_quad5_i ,
781  gt_qpllrefclk_quad5_in => gt_qpllrefclk_quad5_i ,
782 --____________________________COMMON PORTS ,_______________________________}
783 --------------------}
784  tx_out_clk => tx_out_clk_i
785 
786  );
787 
788  end STRUCTURE;
efex_aurora_hub2_CLOCK_MODULE
Definition: efex_aurora_hub2_clock_module.vhd:69
efex_aurora_hub2_SUPPORT_RESET_LOGIC
Definition: efex_aurora_hub2_support_reset_logic.vhd:68
efex_aurora_hub2_gt_common_wrapper
Definition: efex_aurora_hub2_gt_common_wrapper.vhd:61
efex_aurora_hub2_support.STRUCTURE
Definition: efex_aurora_hub2_support.vhd:221
efex_aurora_hub2_support
Definition: efex_aurora_hub2_support.vhd:61
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