efex_aurora_hub2_CLOCK_MODULE Entity Reference

Inheritance diagram for efex_aurora_hub2_CLOCK_MODULE:

Entities
MAPPED	architecture

Libraries
IEEE
UNISIM

Use Clauses
STD_LOGIC_1164
NUMERIC_STD
VCOMPONENTS

Ports
INIT_CLK	in	std_logic
INIT_CLK_O	out	std_logic
GT_CLK	in	std_logic
GT_CLK_LOCKED	in	std_logic
USER_CLK	out	std_logic
SYNC_CLK	out	std_logic
PLL_NOT_LOCKED	out	std_logic

Detailed Description

Definition at line 69 of file efex_aurora_hub2_clock_module.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_clock_module.vhd