efex_aurora_hub2_clock_module.vhd

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--
 
--
--  CLOCK_MODULE
--
--
--
--  Description: A module provided as a convenience for desingners using 4-byte
--               lane Aurora Modules. This module takes the V5 reference clock as
--               input, and produces a fabric clock on a global clock net suitable
--               for driving application logic connected to the Aurora User Interface.
--
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
 
-- synthesis translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- synthesis translate_on
 
entity efex_aurora_hub2_CLOCK_MODULE is
 
    port (
         --   INIT_CLK_P             : in std_logic;
          --  INIT_CLK_N             : in std_logic;
            INIT_CLK               : in std_logic;
            INIT_CLK_O             : out std_logic;
            GT_CLK                 : in std_logic;
            GT_CLK_LOCKED          : in std_logic;
            USER_CLK               : out std_logic;
            SYNC_CLK               : out std_logic;
            PLL_NOT_LOCKED         : out std_logic
 
         );
 
end efex_aurora_hub2_CLOCK_MODULE;
 
architecture MAPPED of efex_aurora_hub2_CLOCK_MODULE is
  attribute core_generation_info           : string;
  attribute core_generation_info of MAPPED : architecture is "efex_aurora_hub2,aurora_8b10b_v11_1_2,{user_interface=AXI_4_Streaming,backchannel_mode=Timer,c_aurora_lanes=4,c_column_used=left,c_gt_clock_1=GTHQ3,c_gt_clock_2=None,c_gt_loc_1=X,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=4,c_gt_loc_15=2,c_gt_loc_16=3,c_gt_loc_17=1,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=2,c_line_rate=64120,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=160300,c_simplex=true,c_simplex_mode=TX,c_stream=false,c_ufc=true,flow_mode=UFC,interface_mode=Framing,dataflow_config=TX-only_Simplex}";
 
    component IBUFDS
        port (
 
                O : out std_ulogic;
                I : in std_ulogic;
                IB : in std_ulogic);
 
    end component;
 
 
-- External Register Declarations --
 
 
    component BUFG
 
        port (
 
                O : out std_ulogic;
                I : in  std_ulogic
 
             );
 
    end component;
 
    signal  user_clk_i     : std_logic;
    signal INIT_CLK_I       : std_logic;
 
begin
 
 
 
    USER_CLK       <= user_clk_i;
    SYNC_CLK       <= user_clk_i;
    PLL_NOT_LOCKED <= not GT_CLK_LOCKED;
 
    -- The User Clock is distributed on a global clock net.
    user_clk_buf_i : BUFG
 
        port map (
 
                    I => GT_CLK,
                    O => user_clk_i
 
                 );
--      init_clk_ibufg_i :  IBUFDS
--      port map (
--           I  => INIT_CLK_P,
--           IB => INIT_CLK_N,
--           O  => INIT_CLK_I
--               );
 
      init_clk_buf_i : BUFG
      port map 
        (
         -- I  => INIT_CLK_I,
          I  => INIT_CLK,
          O  => INIT_CLK_O
        );
 
end MAPPED;