MAPPED Architecture Reference

Components
IBUFDS
BUFG

Signals
user_clk_i	std_logic
INIT_CLK_I	std_logic

Attributes
core_generation_info	string
core_generation_info	architecture is " efex_aurora_hub2 , aurora_8b10b_v11_1_2 , {user_interface = AXI_4_Streaming , backchannel_mode = Timer , c_aurora_lanes = 4 , c_column_used = left , c_gt_clock_1 = GTHQ3 , c_gt_clock_2 = None , c_gt_loc_1 = X , c_gt_loc_10 = X , c_gt_loc_11 = X , c_gt_loc_12 = X , c_gt_loc_13 = X , c_gt_loc_14 = 4 , c_gt_loc_15 = 2 , c_gt_loc_16 = 3 , c_gt_loc_17 = 1 , c_gt_loc_18 = X , c_gt_loc_19 = X , c_gt_loc_2 = X , c_gt_loc_20 = X , c_gt_loc_21 = X , c_gt_loc_22 = X , c_gt_loc_23 = X , c_gt_loc_24 = X , c_gt_loc_25 = X , c_gt_loc_26 = X , c_gt_loc_27 = X , c_gt_loc_28 = X , c_gt_loc_29 = X , c_gt_loc_3 = X , c_gt_loc_30 = X , c_gt_loc_31 = X , c_gt_loc_32 = X , c_gt_loc_33 = X , c_gt_loc_34 = X , c_gt_loc_35 = X , c_gt_loc_36 = X , c_gt_loc_37 = X , c_gt_loc_38 = X , c_gt_loc_39 = X , c_gt_loc_4 = X , c_gt_loc_40 = X , c_gt_loc_41 = X , c_gt_loc_42 = X , c_gt_loc_43 = X , c_gt_loc_44 = X , c_gt_loc_45 = X , c_gt_loc_46 = X , c_gt_loc_47 = X , c_gt_loc_48 = X , c_gt_loc_5 = X , c_gt_loc_6 = X , c_gt_loc_7 = X , c_gt_loc_8 = X , c_gt_loc_9 = X , c_lane_width = 2 , c_line_rate = 64120 , c_nfc = false , c_nfc_mode = IMM , c_refclk_frequency = 160300 , c_simplex = true , c_simplex_mode = TX , c_stream = false , c_ufc = true , flow_mode = UFC , interface_mode = Framing , dataflow_config = TX-only_Simplex} "

Instantiations
user_clk_buf_i	bufg
init_clk_buf_i	bufg

Detailed Description

Definition at line 86 of file efex_aurora_hub2_clock_module.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/control_fpga/src/aurora/efex_aurora_hub2_clock_module.vhd