eFEX firmware  1.7.3
ATLAS l1-calo - electron and tau feature extraction firmware for eFEX boards

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egInputMultiplexer Entity Reference

Input Data Multiplexer for eg: addresses SuperCells to the correct sum area. More...

Inheritance diagram for egInputMultiplexer:
AlgoCore_eg TopAlgoModule IPBusTopAlgoModule data_path_block top_efex_processor

Entities

Behavioral  architecture
 Input Data Multiplexer for eg: addresses SuperCells to the correct sum area. More...
 

Libraries

IEEE 
work 

Use Clauses

STD_LOGIC_1164 
NUMERIC_STD 
DataTypes  Package <DataTypes>

Ports

CLK   in   std_logic
  200 MHz clock
IN_glob_Position   in   AlgoRegister := ( others = > ' 0 ' )
IN_Seed   in   std_logic_vector ( 1 downto 0 )
IN_UpNotDown   in   std_logic
IN_Towers   in   TriggerTowers ( 8 downto 0 )
OUT_EnergyL0   out   DataWords ( 1 downto 0 )
OUT_EnergyL1   out   DataWords ( 5 downto 0 )
OUT_EnergyL2   out   DataWords ( 5 downto 0 )
OUT_EnergyL3   out   DataWords ( 1 downto 0 )
OUT_REtaCoreData   out   DataWords ( 5 downto 0 )
OUT_REtaEnvData   out   DataWords ( 14 downto 0 )
OUT_WsCoreData   out   DataWords ( 11 downto 0 )
OUT_WsEnvData   out   DataWords ( 14 downto 0 )
OUT_HadCoreData   out   DataWords ( 17 downto 0 )
OUT_HadEnvDataL1   out   DataWords ( 5 downto 0 )
OUT_HadEnvDataL2   out   DataWords ( 5 downto 0 )
OUT_HadEnvDataL03   out   DataWords ( 1 downto 0 )

Detailed Description

Input Data Multiplexer for eg: addresses SuperCells to the correct sum area.

The selector of this mux is the seed of the cluster (IN_Seed) plus the phi asimmetry (IN_UpNotDown). According to these values, all the supercells contained in the 9 TTs are addressed to the proper place.

This mux is registerd and the latency is 2 clock cycles, to mach the seed finder.

Author
Francesco Gonnella

Definition at line 19 of file egInputMultiplexer.vhd.


The documentation for this class was generated from the following file: