Behavioral Architecture Reference

Input Data Multiplexer for eg: addresses SuperCells to the correct sum area. More...

Processes
PROCESS_3	( CLK )

Signals
Selector	std_logic_vector ( 2 downto 0 )
ShiftTowers	TriggerTowers ( 8 downto 0 ) := ( others = > ZERO_TRIGGER_TOWER )
ShiftTowers2	TriggerTowers ( 8 downto 0 ) := ( others = > ZERO_TRIGGER_TOWER )
OutEnergyL0	DataWords ( OUT_EnergyL0 ) := ( others = > ( others = > ' 0 ' ) )
OutEnergyL1	DataWords ( OUT_EnergyL1 ) := ( others = > ( others = > ' 0 ' ) )
OutEnergyL2	DataWords ( OUT_EnergyL2 ) := ( others = > ( others = > ' 0 ' ) )
OutEnergyL3	DataWords ( OUT_EnergyL3 ) := ( others = > ( others = > ' 0 ' ) )
OutREtaCoreData	DataWords ( OUT_REtaCoreData ) := ( others = > ( others = > ' 0 ' ) )
OutREtaEnvData	DataWords ( OUT_REtaEnvData ) := ( others = > ( others = > ' 0 ' ) )
OutWsCoreData	DataWords ( OUT_WsCoreData ) := ( others = > ( others = > ' 0 ' ) )
OutWsEnvData	DataWords ( OUT_WsEnvData ) := ( others = > ( others = > ' 0 ' ) )
OutHadCoreData	DataWords ( OUT_HadCoreData ) := ( others = > ( others = > ' 0 ' ) )
OutHadEnvDataL1	DataWords ( OUT_HadEnvDataL1 ) := ( others = > ( others = > ' 0 ' ) )
OutHadEnvDataL2	DataWords ( OUT_HadEnvDataL2 ) := ( others = > ( others = > ' 0 ' ) )
OutHadEnvDataL03	DataWords ( OUT_HadEnvDataL03 ) := ( others = > ( others = > ' 0 ' ) )
Edge	std_logic
selector2	std_logic_vector ( 1 downto 0 )

Detailed Description

Input Data Multiplexer for eg: addresses SuperCells to the correct sum area.

The selector of this mux is the seed of the cluster (IN_Seed) plus the phi asimmetry (IN_UpNotDown). According to these values, all the supercells contained in the 9 TTs are addressed to the proper place.

This mux is registerd and the latency is 2 clock cycles, to mach the seed finder.

Author

Francesco Gonnella

Definition at line 48 of file egInputMultiplexer.vhd.

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The documentation for this class was generated from the following file:

• Algorithm/hdl/egInputMultiplexer.vhd