mgt_playback_ram_wrapper Entity Reference

Wrapper for the input spy/playback RAM of the MGT. More...

Inheritance diagram for mgt_playback_ram_wrapper:

Entities
rtl	architecture
	Wrapper for the input spy/playback RAM of the MGT. More...

Libraries
IEEE
ipbus_lib

Use Clauses
STD_LOGIC_1164
numeric_std
ipbus

Generics
DISABLE	std_logic := ' 0 '

Ports
clk_ipb	in	std_logic
		ipbus clock
rst	in	std_logic
		reset
ipb_in	in	ipb_wbus
		ipbus data in
ipb_out	out	ipb_rbus
		ipbus data out
rdy	in	std_logic
		ready
bcr	in	std_logic
		bcr
ttc_clk	in	std_logic
		ttc clock of 40 MHz
din	in	std_logic_vector ( 31 downto 0 )
		data in
we	in	std_logic := ' 0 '
		write en
q	out	std_logic_vector ( 227 downto 0 )
		data out

Detailed Description

Wrapper for the input spy/playback RAM of the MGT.

The data will be writen through IPbs.

Author

Mohammed Siyad

Francesco Gonnella

Definition at line 18 of file mgt_playback_ram_wrapper.vhd.

---

The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_playback_ram_wrapper.vhd