rtl Architecture Reference

Wrapper for the input spy/playback RAM of the MGT. More...

Processes
IPBUS_RAM	( clk_ipb )

Components
mgt_playback_ram

Signals
ack	std_logic
ack2	std_logic
kchar_i	std_logic
enb	std_logic
addr	std_logic_vector ( 3 downto 0 )
ipbus_write	std_logic_vector ( 0 downto 0 )
write_enable	std_logic_vector ( 0 downto 0 )
ipb_out_int	std_logic_vector ( 31 downto 0 )
q_int	std_logic_vector ( 255 downto 0 )

Instantiations
playback_ram	mgt_playback_ram
sm_playback	ctrl_playback_ram <Entity ctrl_playback_ram>

Detailed Description

Wrapper for the input spy/playback RAM of the MGT.

The data will be writen through IPbs.

Author

Mohammed Siyad

Francesco Gonnella

Definition at line 47 of file mgt_playback_ram_wrapper.vhd.

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The documentation for this class was generated from the following file:

• Infrastructure/process_Fpga_common/src/MGT/vhdl/mgt_playback_ram_wrapper.vhd