spi32_8_control.vhd File Reference

icontroller for SPI interface PLL chips of FTM /eFEX More...

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Entities
spi32_8_control	entity
	icontroller for SPI interface PLL chips of FTM /eFEX More...
rtl	architecture
	icontroller for SPI interface PLL chips of FTM /eFEX More...

Detailed Description

icontroller for SPI interface PLL chips of FTM /eFEX

Buffer RAMs are 32 bits wide. The word at outgoing buffer(index) is read and a spi frame sent. Returning data is written into incoming buffer(index), the first word/byte can be discarded. Index' increments until 'transfer_count' words/bytes are transfered. Transfer count either in bytes or words, set by BYTE_SPI switch.

Author

Richard Staley

Definition in file spi32_8_control.vhd.