RTL Architecture Reference

Functions
integer	get_cdrlock_time ( is_sim: in in integer )

Processes
gt0_cdrlock_timeout	( SYSCLK_IN )
gt1_cdrlock_timeout	( SYSCLK_IN )
gt2_cdrlock_timeout	( SYSCLK_IN )
gt3_cdrlock_timeout	( SYSCLK_IN )
gt4_cdrlock_timeout	( SYSCLK_IN )
gt5_cdrlock_timeout	( SYSCLK_IN )
gt6_cdrlock_timeout	( SYSCLK_IN )
gt7_cdrlock_timeout	( SYSCLK_IN )

Components
CON_2Quads_6g4_multi_gt	<Entity CON_2Quads_6g4_multi_gt>
CON_2Quads_6g4_TX_STARTUP_FSM	<Entity CON_2Quads_6g4_TX_STARTUP_FSM>
CON_2Quads_6g4_RX_STARTUP_FSM	<Entity CON_2Quads_6g4_RX_STARTUP_FSM>
CON_2Quads_6g4_AUTO_PHASE_ALIGN
CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN	<Entity CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN>
CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN	<Entity CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN>

Constants
DLY	time := 1 ns
RX_CDRLOCK_TIME	integer := get_cdrlock_time ( EXAMPLE_SIMULATION )
WAIT_TIME_CDRLOCK	integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD

Signals
gt0_txpmaresetdone_i	std_logic
gt0_rxpmaresetdone_i	std_logic
gt0_txresetdone_i	std_logic
gt0_rxresetdone_i	std_logic
gt0_txresetdone_ii	std_logic
gt0_rxresetdone_ii	std_logic
gt0_gttxreset_i	std_logic
gt0_gttxreset_t	std_logic
gt0_gtrxreset_i	std_logic
gt0_gtrxreset_t	std_logic
gt0_rxdfelpmreset_i	std_logic
gt0_txuserrdy_i	std_logic
gt0_txuserrdy_t	std_logic
gt0_rxuserrdy_i	std_logic
gt0_rxuserrdy_t	std_logic
gt0_rxdfeagchold_i	std_logic
gt0_rxdfelfhold_i	std_logic
gt0_rxlpmlfhold_i	std_logic
gt0_rxlpmhfhold_i	std_logic
gt1_txpmaresetdone_i	std_logic
gt1_rxpmaresetdone_i	std_logic
gt1_txresetdone_i	std_logic
gt1_rxresetdone_i	std_logic
gt1_txresetdone_ii	std_logic
gt1_rxresetdone_ii	std_logic
gt1_gttxreset_i	std_logic
gt1_gttxreset_t	std_logic
gt1_gtrxreset_i	std_logic
gt1_gtrxreset_t	std_logic
gt1_rxdfelpmreset_i	std_logic
gt1_txuserrdy_i	std_logic
gt1_txuserrdy_t	std_logic
gt1_rxuserrdy_i	std_logic
gt1_rxuserrdy_t	std_logic
gt1_rxdfeagchold_i	std_logic
gt1_rxdfelfhold_i	std_logic
gt1_rxlpmlfhold_i	std_logic
gt1_rxlpmhfhold_i	std_logic
gt2_txpmaresetdone_i	std_logic
gt2_rxpmaresetdone_i	std_logic
gt2_txresetdone_i	std_logic
gt2_rxresetdone_i	std_logic
gt2_txresetdone_ii	std_logic
gt2_rxresetdone_ii	std_logic
gt2_gttxreset_i	std_logic
gt2_gttxreset_t	std_logic
gt2_gtrxreset_i	std_logic
gt2_gtrxreset_t	std_logic
gt2_rxdfelpmreset_i	std_logic
gt2_txuserrdy_i	std_logic
gt2_txuserrdy_t	std_logic
gt2_rxuserrdy_i	std_logic
gt2_rxuserrdy_t	std_logic
gt2_rxdfeagchold_i	std_logic
gt2_rxdfelfhold_i	std_logic
gt2_rxlpmlfhold_i	std_logic
gt2_rxlpmhfhold_i	std_logic
gt3_txpmaresetdone_i	std_logic
gt3_rxpmaresetdone_i	std_logic
gt3_txresetdone_i	std_logic
gt3_rxresetdone_i	std_logic
gt3_txresetdone_ii	std_logic
gt3_rxresetdone_ii	std_logic
gt3_gttxreset_i	std_logic
gt3_gttxreset_t	std_logic
gt3_gtrxreset_i	std_logic
gt3_gtrxreset_t	std_logic
gt3_rxdfelpmreset_i	std_logic
gt3_txuserrdy_i	std_logic
gt3_txuserrdy_t	std_logic
gt3_rxuserrdy_i	std_logic
gt3_rxuserrdy_t	std_logic
gt3_rxdfeagchold_i	std_logic
gt3_rxdfelfhold_i	std_logic
gt3_rxlpmlfhold_i	std_logic
gt3_rxlpmhfhold_i	std_logic
gt4_txpmaresetdone_i	std_logic
gt4_rxpmaresetdone_i	std_logic
gt4_txresetdone_i	std_logic
gt4_rxresetdone_i	std_logic
gt4_txresetdone_ii	std_logic
gt4_rxresetdone_ii	std_logic
gt4_gttxreset_i	std_logic
gt4_gttxreset_t	std_logic
gt4_gtrxreset_i	std_logic
gt4_gtrxreset_t	std_logic
gt4_rxdfelpmreset_i	std_logic
gt4_txuserrdy_i	std_logic
gt4_txuserrdy_t	std_logic
gt4_rxuserrdy_i	std_logic
gt4_rxuserrdy_t	std_logic
gt4_rxdfeagchold_i	std_logic
gt4_rxdfelfhold_i	std_logic
gt4_rxlpmlfhold_i	std_logic
gt4_rxlpmhfhold_i	std_logic
gt5_txpmaresetdone_i	std_logic
gt5_rxpmaresetdone_i	std_logic
gt5_txresetdone_i	std_logic
gt5_rxresetdone_i	std_logic
gt5_txresetdone_ii	std_logic
gt5_rxresetdone_ii	std_logic
gt5_gttxreset_i	std_logic
gt5_gttxreset_t	std_logic
gt5_gtrxreset_i	std_logic
gt5_gtrxreset_t	std_logic
gt5_rxdfelpmreset_i	std_logic
gt5_txuserrdy_i	std_logic
gt5_txuserrdy_t	std_logic
gt5_rxuserrdy_i	std_logic
gt5_rxuserrdy_t	std_logic
gt5_rxdfeagchold_i	std_logic
gt5_rxdfelfhold_i	std_logic
gt5_rxlpmlfhold_i	std_logic
gt5_rxlpmhfhold_i	std_logic
gt6_txpmaresetdone_i	std_logic
gt6_rxpmaresetdone_i	std_logic
gt6_txresetdone_i	std_logic
gt6_rxresetdone_i	std_logic
gt6_txresetdone_ii	std_logic
gt6_rxresetdone_ii	std_logic
gt6_gttxreset_i	std_logic
gt6_gttxreset_t	std_logic
gt6_gtrxreset_i	std_logic
gt6_gtrxreset_t	std_logic
gt6_rxdfelpmreset_i	std_logic
gt6_txuserrdy_i	std_logic
gt6_txuserrdy_t	std_logic
gt6_rxuserrdy_i	std_logic
gt6_rxuserrdy_t	std_logic
gt6_rxdfeagchold_i	std_logic
gt6_rxdfelfhold_i	std_logic
gt6_rxlpmlfhold_i	std_logic
gt6_rxlpmhfhold_i	std_logic
gt7_txpmaresetdone_i	std_logic
gt7_rxpmaresetdone_i	std_logic
gt7_txresetdone_i	std_logic
gt7_rxresetdone_i	std_logic
gt7_txresetdone_ii	std_logic
gt7_rxresetdone_ii	std_logic
gt7_gttxreset_i	std_logic
gt7_gttxreset_t	std_logic
gt7_gtrxreset_i	std_logic
gt7_gtrxreset_t	std_logic
gt7_rxdfelpmreset_i	std_logic
gt7_txuserrdy_i	std_logic
gt7_txuserrdy_t	std_logic
gt7_rxuserrdy_i	std_logic
gt7_rxuserrdy_t	std_logic
gt7_rxdfeagchold_i	std_logic
gt7_rxdfelfhold_i	std_logic
gt7_rxlpmlfhold_i	std_logic
gt7_rxlpmhfhold_i	std_logic
gt0_qpllreset_i	std_logic
gt0_qpllreset_t	std_logic
gt0_qpllrefclklost_i	std_logic
gt0_qplllock_i	std_logic
gt1_qpllreset_i	std_logic
gt1_qpllreset_t	std_logic
gt1_qpllrefclklost_i	std_logic
gt1_qplllock_i	std_logic
tied_to_ground_i	std_logic
tied_to_vcc_i	std_logic
gt0_txphaligndone_i	std_logic
gt0_txdlysreset_i	std_logic
gt0_txdlysresetdone_i	std_logic
gt0_txphdlyreset_i	std_logic
gt0_txphalignen_i	std_logic
gt0_txdlyen_i	std_logic
gt0_txphalign_i	std_logic
gt0_txphinit_i	std_logic
gt0_txphinitdone_i	std_logic
gt0_run_tx_phalignment_i	std_logic
gt0_rst_tx_phalignment_i	std_logic
gt0_tx_phalignment_done_i	std_logic
gt0_txoutclk_i	std_logic
gt0_rxoutclk_i	std_logic
gt0_rxoutclk_i2	std_logic
gt0_txoutclk_i2	std_logic
gt0_recclk_stable_i	std_logic
gt0_rx_cdrlocked	std_logic
gt0_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt0_rxphaligndone_i	std_logic
gt0_rxdlysreset_i	std_logic
gt0_rxdlysresetdone_i	std_logic
gt0_rxphdlyreset_i	std_logic
gt0_rxphalignen_i	std_logic
gt0_rxdlyen_i	std_logic
gt0_rxphalign_i	std_logic
gt0_run_rx_phalignment_i	std_logic
gt0_rst_rx_phalignment_i	std_logic
gt0_rx_phalignment_done_i	std_logic
gt1_txphaligndone_i	std_logic
gt1_txdlysreset_i	std_logic
gt1_txdlysresetdone_i	std_logic
gt1_txphdlyreset_i	std_logic
gt1_txphalignen_i	std_logic
gt1_txdlyen_i	std_logic
gt1_txphalign_i	std_logic
gt1_txphinit_i	std_logic
gt1_txphinitdone_i	std_logic
gt1_run_tx_phalignment_i	std_logic
gt1_rst_tx_phalignment_i	std_logic
gt1_tx_phalignment_done_i	std_logic
gt1_txoutclk_i	std_logic
gt1_rxoutclk_i	std_logic
gt1_rxoutclk_i2	std_logic
gt1_txoutclk_i2	std_logic
gt1_recclk_stable_i	std_logic
gt1_rx_cdrlocked	std_logic
gt1_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt1_rxphaligndone_i	std_logic
gt1_rxdlysreset_i	std_logic
gt1_rxdlysresetdone_i	std_logic
gt1_rxphdlyreset_i	std_logic
gt1_rxphalignen_i	std_logic
gt1_rxdlyen_i	std_logic
gt1_rxphalign_i	std_logic
gt1_run_rx_phalignment_i	std_logic
gt1_rst_rx_phalignment_i	std_logic
gt1_rx_phalignment_done_i	std_logic
gt2_txphaligndone_i	std_logic
gt2_txdlysreset_i	std_logic
gt2_txdlysresetdone_i	std_logic
gt2_txphdlyreset_i	std_logic
gt2_txphalignen_i	std_logic
gt2_txdlyen_i	std_logic
gt2_txphalign_i	std_logic
gt2_txphinit_i	std_logic
gt2_txphinitdone_i	std_logic
gt2_run_tx_phalignment_i	std_logic
gt2_rst_tx_phalignment_i	std_logic
gt2_tx_phalignment_done_i	std_logic
gt2_txoutclk_i	std_logic
gt2_rxoutclk_i	std_logic
gt2_rxoutclk_i2	std_logic
gt2_txoutclk_i2	std_logic
gt2_recclk_stable_i	std_logic
gt2_rx_cdrlocked	std_logic
gt2_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt2_rxphaligndone_i	std_logic
gt2_rxdlysreset_i	std_logic
gt2_rxdlysresetdone_i	std_logic
gt2_rxphdlyreset_i	std_logic
gt2_rxphalignen_i	std_logic
gt2_rxdlyen_i	std_logic
gt2_rxphalign_i	std_logic
gt2_run_rx_phalignment_i	std_logic
gt2_rst_rx_phalignment_i	std_logic
gt2_rx_phalignment_done_i	std_logic
gt3_txphaligndone_i	std_logic
gt3_txdlysreset_i	std_logic
gt3_txdlysresetdone_i	std_logic
gt3_txphdlyreset_i	std_logic
gt3_txphalignen_i	std_logic
gt3_txdlyen_i	std_logic
gt3_txphalign_i	std_logic
gt3_txphinit_i	std_logic
gt3_txphinitdone_i	std_logic
gt3_run_tx_phalignment_i	std_logic
gt3_rst_tx_phalignment_i	std_logic
gt3_tx_phalignment_done_i	std_logic
gt3_txoutclk_i	std_logic
gt3_rxoutclk_i	std_logic
gt3_rxoutclk_i2	std_logic
gt3_txoutclk_i2	std_logic
gt3_recclk_stable_i	std_logic
gt3_rx_cdrlocked	std_logic
gt3_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt3_rxphaligndone_i	std_logic
gt3_rxdlysreset_i	std_logic
gt3_rxdlysresetdone_i	std_logic
gt3_rxphdlyreset_i	std_logic
gt3_rxphalignen_i	std_logic
gt3_rxdlyen_i	std_logic
gt3_rxphalign_i	std_logic
gt3_run_rx_phalignment_i	std_logic
gt3_rst_rx_phalignment_i	std_logic
gt3_rx_phalignment_done_i	std_logic
gt4_txphaligndone_i	std_logic
gt4_txdlysreset_i	std_logic
gt4_txdlysresetdone_i	std_logic
gt4_txphdlyreset_i	std_logic
gt4_txphalignen_i	std_logic
gt4_txdlyen_i	std_logic
gt4_txphalign_i	std_logic
gt4_txphinit_i	std_logic
gt4_txphinitdone_i	std_logic
gt4_run_tx_phalignment_i	std_logic
gt4_rst_tx_phalignment_i	std_logic
gt4_tx_phalignment_done_i	std_logic
gt4_txoutclk_i	std_logic
gt4_rxoutclk_i	std_logic
gt4_rxoutclk_i2	std_logic
gt4_txoutclk_i2	std_logic
gt4_recclk_stable_i	std_logic
gt4_rx_cdrlocked	std_logic
gt4_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt4_rxphaligndone_i	std_logic
gt4_rxdlysreset_i	std_logic
gt4_rxdlysresetdone_i	std_logic
gt4_rxphdlyreset_i	std_logic
gt4_rxphalignen_i	std_logic
gt4_rxdlyen_i	std_logic
gt4_rxphalign_i	std_logic
gt4_run_rx_phalignment_i	std_logic
gt4_rst_rx_phalignment_i	std_logic
gt4_rx_phalignment_done_i	std_logic
gt5_txphaligndone_i	std_logic
gt5_txdlysreset_i	std_logic
gt5_txdlysresetdone_i	std_logic
gt5_txphdlyreset_i	std_logic
gt5_txphalignen_i	std_logic
gt5_txdlyen_i	std_logic
gt5_txphalign_i	std_logic
gt5_txphinit_i	std_logic
gt5_txphinitdone_i	std_logic
gt5_run_tx_phalignment_i	std_logic
gt5_rst_tx_phalignment_i	std_logic
gt5_tx_phalignment_done_i	std_logic
gt5_txoutclk_i	std_logic
gt5_rxoutclk_i	std_logic
gt5_rxoutclk_i2	std_logic
gt5_txoutclk_i2	std_logic
gt5_recclk_stable_i	std_logic
gt5_rx_cdrlocked	std_logic
gt5_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt5_rxphaligndone_i	std_logic
gt5_rxdlysreset_i	std_logic
gt5_rxdlysresetdone_i	std_logic
gt5_rxphdlyreset_i	std_logic
gt5_rxphalignen_i	std_logic
gt5_rxdlyen_i	std_logic
gt5_rxphalign_i	std_logic
gt5_run_rx_phalignment_i	std_logic
gt5_rst_rx_phalignment_i	std_logic
gt5_rx_phalignment_done_i	std_logic
gt6_txphaligndone_i	std_logic
gt6_txdlysreset_i	std_logic
gt6_txdlysresetdone_i	std_logic
gt6_txphdlyreset_i	std_logic
gt6_txphalignen_i	std_logic
gt6_txdlyen_i	std_logic
gt6_txphalign_i	std_logic
gt6_txphinit_i	std_logic
gt6_txphinitdone_i	std_logic
gt6_run_tx_phalignment_i	std_logic
gt6_rst_tx_phalignment_i	std_logic
gt6_tx_phalignment_done_i	std_logic
gt6_txoutclk_i	std_logic
gt6_rxoutclk_i	std_logic
gt6_rxoutclk_i2	std_logic
gt6_txoutclk_i2	std_logic
gt6_recclk_stable_i	std_logic
gt6_rx_cdrlocked	std_logic
gt6_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt6_rxphaligndone_i	std_logic
gt6_rxdlysreset_i	std_logic
gt6_rxdlysresetdone_i	std_logic
gt6_rxphdlyreset_i	std_logic
gt6_rxphalignen_i	std_logic
gt6_rxdlyen_i	std_logic
gt6_rxphalign_i	std_logic
gt6_run_rx_phalignment_i	std_logic
gt6_rst_rx_phalignment_i	std_logic
gt6_rx_phalignment_done_i	std_logic
gt7_txphaligndone_i	std_logic
gt7_txdlysreset_i	std_logic
gt7_txdlysresetdone_i	std_logic
gt7_txphdlyreset_i	std_logic
gt7_txphalignen_i	std_logic
gt7_txdlyen_i	std_logic
gt7_txphalign_i	std_logic
gt7_txphinit_i	std_logic
gt7_txphinitdone_i	std_logic
gt7_run_tx_phalignment_i	std_logic
gt7_rst_tx_phalignment_i	std_logic
gt7_tx_phalignment_done_i	std_logic
gt7_txoutclk_i	std_logic
gt7_rxoutclk_i	std_logic
gt7_rxoutclk_i2	std_logic
gt7_txoutclk_i2	std_logic
gt7_recclk_stable_i	std_logic
gt7_rx_cdrlocked	std_logic
gt7_rx_cdrlock_counter	integer range 0 to WAIT_TIME_CDRLOCK := 0
gt7_rxphaligndone_i	std_logic
gt7_rxdlysreset_i	std_logic
gt7_rxdlysresetdone_i	std_logic
gt7_rxphdlyreset_i	std_logic
gt7_rxphalignen_i	std_logic
gt7_rxdlyen_i	std_logic
gt7_rxphalign_i	std_logic
gt7_run_rx_phalignment_i	std_logic
gt7_rst_rx_phalignment_i	std_logic
gt7_rx_phalignment_done_i	std_logic
mstr0_txsyncallin_i	std_logic
U0_TXDLYEN	std_logic_vector ( 3 downto 0 )
U0_TXDLYSRESET	std_logic_vector ( 3 downto 0 )
U0_TXDLYSRESETDONE	std_logic_vector ( 3 downto 0 )
U0_TXPHINIT	std_logic_vector ( 3 downto 0 )
U0_TXPHINITDONE	std_logic_vector ( 3 downto 0 )
U0_TXPHALIGN	std_logic_vector ( 3 downto 0 )
U0_TXPHALIGNDONE	std_logic_vector ( 3 downto 0 )
U0_run_tx_phalignment_i	std_logic
U0_rst_tx_phalignment_i	std_logic
mstr4_txsyncallin_i	std_logic
U4_TXDLYEN	std_logic_vector ( 3 downto 0 )
U4_TXDLYSRESET	std_logic_vector ( 3 downto 0 )
U4_TXDLYSRESETDONE	std_logic_vector ( 3 downto 0 )
U4_TXPHINIT	std_logic_vector ( 3 downto 0 )
U4_TXPHINITDONE	std_logic_vector ( 3 downto 0 )
U4_TXPHALIGN	std_logic_vector ( 3 downto 0 )
U4_TXPHALIGNDONE	std_logic_vector ( 3 downto 0 )
U4_run_tx_phalignment_i	std_logic
U4_rst_tx_phalignment_i	std_logic
rxmstr0_rxsyncallin_i	std_logic
U0_RXDLYEN	std_logic_vector ( 3 downto 0 )
U0_RXDLYSRESET	std_logic_vector ( 3 downto 0 )
U0_RXDLYSRESETDONE	std_logic_vector ( 3 downto 0 )
U0_RXPHALIGN	std_logic_vector ( 3 downto 0 )
U0_RXPHALIGNDONE	std_logic_vector ( 3 downto 0 )
U0_run_rx_phalignment_i	std_logic
U0_rst_rx_phalignment_i	std_logic
rxmstr4_rxsyncallin_i	std_logic
U4_RXDLYEN	std_logic_vector ( 3 downto 0 )
U4_RXDLYSRESET	std_logic_vector ( 3 downto 0 )
U4_RXDLYSRESETDONE	std_logic_vector ( 3 downto 0 )
U4_RXPHALIGN	std_logic_vector ( 3 downto 0 )
U4_RXPHALIGNDONE	std_logic_vector ( 3 downto 0 )
U4_run_rx_phalignment_i	std_logic
U4_rst_rx_phalignment_i	std_logic
rx_cdrlocked	std_logic

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	RTL : architecture is " yes "

Instantiations
con_2quads_6g4_i	CON_2Quads_6g4_multi_gt <Entity CON_2Quads_6g4_multi_gt>
gt0_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt1_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt2_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt3_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt4_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt5_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt6_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt7_txresetfsm_i	CON_2Quads_6g4_TX_STARTUP_FSM <Entity CON_2Quads_6g4_TX_STARTUP_FSM>
gt0_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt1_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt2_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt3_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt4_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt5_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt6_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt7_rxresetfsm_i	CON_2Quads_6g4_RX_STARTUP_FSM <Entity CON_2Quads_6g4_RX_STARTUP_FSM>
gt0_tx_manual_phase_i	CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN <Entity CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN>
gt4_tx_manual_phase_i	CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN <Entity CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN>
gt0_rx_manual_phase_i	CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN <Entity CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN>
gt4_rx_manual_phase_i	CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN <Entity CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN>

Member Function Documentation

get_cdrlock_time()

integer get_cdrlock_time (   is_sim in in integer   )

Function

gt0_cdrlock_timeout()

gt0_cdrlock_timeout

(

SYSCLK_IN

)

gt1_cdrlock_timeout()

gt1_cdrlock_timeout (   SYSCLK_IN   )

Process

gt2_cdrlock_timeout()

gt2_cdrlock_timeout (   SYSCLK_IN   )

Process

gt3_cdrlock_timeout()

gt3_cdrlock_timeout (   SYSCLK_IN   )

Process

gt4_cdrlock_timeout()

gt4_cdrlock_timeout (   SYSCLK_IN   )

Process

gt5_cdrlock_timeout()

gt5_cdrlock_timeout (   SYSCLK_IN   )

Process

gt6_cdrlock_timeout()

gt6_cdrlock_timeout (   SYSCLK_IN   )

Process

gt7_cdrlock_timeout()

gt7_cdrlock_timeout (   SYSCLK_IN   )

Process

Member Data Documentation

CON_2Quads_6g4_AUTO_PHASE_ALIGN

CON_2Quads_6g4_AUTO_PHASE_ALIGN

Component

con_2quads_6g4_i

con_2quads_6g4_i CON_2Quads_6g4_multi_gt

Instantiation

CON_2Quads_6g4_multi_gt

CON_2Quads_6g4_multi_gt

Component

CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN

CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN

Component

CON_2Quads_6g4_RX_STARTUP_FSM

CON_2Quads_6g4_RX_STARTUP_FSM

Component

CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN

CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN

Component

CON_2Quads_6g4_TX_STARTUP_FSM

CON_2Quads_6g4_TX_STARTUP_FSM

Component

DLY

DLY time := 1 ns

Constant

DowngradeIPIdentifiedWarnings [1/2]

DowngradeIPIdentifiedWarnings string

Attribute

DowngradeIPIdentifiedWarnings [2/2]

DowngradeIPIdentifiedWarnings RTL : architecture is " yes "

Attribute

gt0_gtrxreset_i

gt0_gtrxreset_i std_logic

Signal

gt0_gtrxreset_t

gt0_gtrxreset_t std_logic

Signal

gt0_gttxreset_i

gt0_gttxreset_i std_logic

Signal

gt0_gttxreset_t

gt0_gttxreset_t std_logic

Signal

gt0_qplllock_i

gt0_qplllock_i std_logic

Signal

gt0_qpllrefclklost_i

gt0_qpllrefclklost_i std_logic

Signal

gt0_qpllreset_i

gt0_qpllreset_i std_logic

Signal

gt0_qpllreset_t

gt0_qpllreset_t std_logic

Signal

gt0_recclk_stable_i

gt0_recclk_stable_i std_logic

Signal

gt0_rst_rx_phalignment_i

gt0_rst_rx_phalignment_i std_logic

Signal

gt0_rst_tx_phalignment_i

gt0_rst_tx_phalignment_i std_logic

Signal

gt0_run_rx_phalignment_i

gt0_run_rx_phalignment_i std_logic

Signal

gt0_run_tx_phalignment_i

gt0_run_tx_phalignment_i std_logic

Signal

gt0_rx_cdrlock_counter

gt0_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt0_rx_cdrlocked

gt0_rx_cdrlocked std_logic

Signal

gt0_rx_manual_phase_i

gt0_rx_manual_phase_i CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN

Instantiation

gt0_rx_phalignment_done_i

gt0_rx_phalignment_done_i std_logic

Signal

gt0_rxdfeagchold_i

gt0_rxdfeagchold_i std_logic

Signal

gt0_rxdfelfhold_i

gt0_rxdfelfhold_i std_logic

Signal

gt0_rxdfelpmreset_i

gt0_rxdfelpmreset_i std_logic

Signal

gt0_rxdlyen_i

gt0_rxdlyen_i std_logic

Signal

gt0_rxdlysreset_i

gt0_rxdlysreset_i std_logic

Signal

gt0_rxdlysresetdone_i

gt0_rxdlysresetdone_i std_logic

Signal

gt0_rxlpmhfhold_i

gt0_rxlpmhfhold_i std_logic

Signal

gt0_rxlpmlfhold_i

gt0_rxlpmlfhold_i std_logic

Signal

gt0_rxoutclk_i

gt0_rxoutclk_i std_logic

Signal

gt0_rxoutclk_i2

gt0_rxoutclk_i2 std_logic

Signal

gt0_rxphalign_i

gt0_rxphalign_i std_logic

Signal

gt0_rxphaligndone_i

gt0_rxphaligndone_i std_logic

Signal

gt0_rxphalignen_i

gt0_rxphalignen_i std_logic

Signal

gt0_rxphdlyreset_i

gt0_rxphdlyreset_i std_logic

Signal

gt0_rxpmaresetdone_i

gt0_rxpmaresetdone_i std_logic

Signal

gt0_rxresetdone_i

gt0_rxresetdone_i std_logic

Signal

gt0_rxresetdone_ii

gt0_rxresetdone_ii std_logic

Signal

gt0_rxresetfsm_i

gt0_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt0_rxuserrdy_i

gt0_rxuserrdy_i std_logic

Signal

gt0_rxuserrdy_t

gt0_rxuserrdy_t std_logic

Signal

gt0_tx_manual_phase_i

gt0_tx_manual_phase_i CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN

Instantiation

gt0_tx_phalignment_done_i

gt0_tx_phalignment_done_i std_logic

Signal

gt0_txdlyen_i

gt0_txdlyen_i std_logic

Signal

gt0_txdlysreset_i

gt0_txdlysreset_i std_logic

Signal

gt0_txdlysresetdone_i

gt0_txdlysresetdone_i std_logic

Signal

gt0_txoutclk_i

gt0_txoutclk_i std_logic

Signal

gt0_txoutclk_i2

gt0_txoutclk_i2 std_logic

Signal

gt0_txphalign_i

gt0_txphalign_i std_logic

Signal

gt0_txphaligndone_i

gt0_txphaligndone_i std_logic

Signal

gt0_txphalignen_i

gt0_txphalignen_i std_logic

Signal

gt0_txphdlyreset_i

gt0_txphdlyreset_i std_logic

Signal

gt0_txphinit_i

gt0_txphinit_i std_logic

Signal

gt0_txphinitdone_i

gt0_txphinitdone_i std_logic

Signal

gt0_txpmaresetdone_i

gt0_txpmaresetdone_i std_logic

Signal

gt0_txresetdone_i

gt0_txresetdone_i std_logic

Signal

gt0_txresetdone_ii

gt0_txresetdone_ii std_logic

Signal

gt0_txresetfsm_i

gt0_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt0_txuserrdy_i

gt0_txuserrdy_i std_logic

Signal

gt0_txuserrdy_t

gt0_txuserrdy_t std_logic

Signal

gt1_gtrxreset_i

gt1_gtrxreset_i std_logic

Signal

gt1_gtrxreset_t

gt1_gtrxreset_t std_logic

Signal

gt1_gttxreset_i

gt1_gttxreset_i std_logic

Signal

gt1_gttxreset_t

gt1_gttxreset_t std_logic

Signal

gt1_qplllock_i

gt1_qplllock_i std_logic

Signal

gt1_qpllrefclklost_i

gt1_qpllrefclklost_i std_logic

Signal

gt1_qpllreset_i

gt1_qpllreset_i std_logic

Signal

gt1_qpllreset_t

gt1_qpllreset_t std_logic

Signal

gt1_recclk_stable_i

gt1_recclk_stable_i std_logic

Signal

gt1_rst_rx_phalignment_i

gt1_rst_rx_phalignment_i std_logic

Signal

gt1_rst_tx_phalignment_i

gt1_rst_tx_phalignment_i std_logic

Signal

gt1_run_rx_phalignment_i

gt1_run_rx_phalignment_i std_logic

Signal

gt1_run_tx_phalignment_i

gt1_run_tx_phalignment_i std_logic

Signal

gt1_rx_cdrlock_counter

gt1_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt1_rx_cdrlocked

gt1_rx_cdrlocked std_logic

Signal

gt1_rx_phalignment_done_i

gt1_rx_phalignment_done_i std_logic

Signal

gt1_rxdfeagchold_i

gt1_rxdfeagchold_i std_logic

Signal

gt1_rxdfelfhold_i

gt1_rxdfelfhold_i std_logic

Signal

gt1_rxdfelpmreset_i

gt1_rxdfelpmreset_i std_logic

Signal

gt1_rxdlyen_i

gt1_rxdlyen_i std_logic

Signal

gt1_rxdlysreset_i

gt1_rxdlysreset_i std_logic

Signal

gt1_rxdlysresetdone_i

gt1_rxdlysresetdone_i std_logic

Signal

gt1_rxlpmhfhold_i

gt1_rxlpmhfhold_i std_logic

Signal

gt1_rxlpmlfhold_i

gt1_rxlpmlfhold_i std_logic

Signal

gt1_rxoutclk_i

gt1_rxoutclk_i std_logic

Signal

gt1_rxoutclk_i2

gt1_rxoutclk_i2 std_logic

Signal

gt1_rxphalign_i

gt1_rxphalign_i std_logic

Signal

gt1_rxphaligndone_i

gt1_rxphaligndone_i std_logic

Signal

gt1_rxphalignen_i

gt1_rxphalignen_i std_logic

Signal

gt1_rxphdlyreset_i

gt1_rxphdlyreset_i std_logic

Signal

gt1_rxpmaresetdone_i

gt1_rxpmaresetdone_i std_logic

Signal

gt1_rxresetdone_i

gt1_rxresetdone_i std_logic

Signal

gt1_rxresetdone_ii

gt1_rxresetdone_ii std_logic

Signal

gt1_rxresetfsm_i

gt1_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt1_rxuserrdy_i

gt1_rxuserrdy_i std_logic

Signal

gt1_rxuserrdy_t

gt1_rxuserrdy_t std_logic

Signal

gt1_tx_phalignment_done_i

gt1_tx_phalignment_done_i std_logic

Signal

gt1_txdlyen_i

gt1_txdlyen_i std_logic

Signal

gt1_txdlysreset_i

gt1_txdlysreset_i std_logic

Signal

gt1_txdlysresetdone_i

gt1_txdlysresetdone_i std_logic

Signal

gt1_txoutclk_i

gt1_txoutclk_i std_logic

Signal

gt1_txoutclk_i2

gt1_txoutclk_i2 std_logic

Signal

gt1_txphalign_i

gt1_txphalign_i std_logic

Signal

gt1_txphaligndone_i

gt1_txphaligndone_i std_logic

Signal

gt1_txphalignen_i

gt1_txphalignen_i std_logic

Signal

gt1_txphdlyreset_i

gt1_txphdlyreset_i std_logic

Signal

gt1_txphinit_i

gt1_txphinit_i std_logic

Signal

gt1_txphinitdone_i

gt1_txphinitdone_i std_logic

Signal

gt1_txpmaresetdone_i

gt1_txpmaresetdone_i std_logic

Signal

gt1_txresetdone_i

gt1_txresetdone_i std_logic

Signal

gt1_txresetdone_ii

gt1_txresetdone_ii std_logic

Signal

gt1_txresetfsm_i

gt1_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt1_txuserrdy_i

gt1_txuserrdy_i std_logic

Signal

gt1_txuserrdy_t

gt1_txuserrdy_t std_logic

Signal

gt2_gtrxreset_i

gt2_gtrxreset_i std_logic

Signal

gt2_gtrxreset_t

gt2_gtrxreset_t std_logic

Signal

gt2_gttxreset_i

gt2_gttxreset_i std_logic

Signal

gt2_gttxreset_t

gt2_gttxreset_t std_logic

Signal

gt2_recclk_stable_i

gt2_recclk_stable_i std_logic

Signal

gt2_rst_rx_phalignment_i

gt2_rst_rx_phalignment_i std_logic

Signal

gt2_rst_tx_phalignment_i

gt2_rst_tx_phalignment_i std_logic

Signal

gt2_run_rx_phalignment_i

gt2_run_rx_phalignment_i std_logic

Signal

gt2_run_tx_phalignment_i

gt2_run_tx_phalignment_i std_logic

Signal

gt2_rx_cdrlock_counter

gt2_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt2_rx_cdrlocked

gt2_rx_cdrlocked std_logic

Signal

gt2_rx_phalignment_done_i

gt2_rx_phalignment_done_i std_logic

Signal

gt2_rxdfeagchold_i

gt2_rxdfeagchold_i std_logic

Signal

gt2_rxdfelfhold_i

gt2_rxdfelfhold_i std_logic

Signal

gt2_rxdfelpmreset_i

gt2_rxdfelpmreset_i std_logic

Signal

gt2_rxdlyen_i

gt2_rxdlyen_i std_logic

Signal

gt2_rxdlysreset_i

gt2_rxdlysreset_i std_logic

Signal

gt2_rxdlysresetdone_i

gt2_rxdlysresetdone_i std_logic

Signal

gt2_rxlpmhfhold_i

gt2_rxlpmhfhold_i std_logic

Signal

gt2_rxlpmlfhold_i

gt2_rxlpmlfhold_i std_logic

Signal

gt2_rxoutclk_i

gt2_rxoutclk_i std_logic

Signal

gt2_rxoutclk_i2

gt2_rxoutclk_i2 std_logic

Signal

gt2_rxphalign_i

gt2_rxphalign_i std_logic

Signal

gt2_rxphaligndone_i

gt2_rxphaligndone_i std_logic

Signal

gt2_rxphalignen_i

gt2_rxphalignen_i std_logic

Signal

gt2_rxphdlyreset_i

gt2_rxphdlyreset_i std_logic

Signal

gt2_rxpmaresetdone_i

gt2_rxpmaresetdone_i std_logic

Signal

gt2_rxresetdone_i

gt2_rxresetdone_i std_logic

Signal

gt2_rxresetdone_ii

gt2_rxresetdone_ii std_logic

Signal

gt2_rxresetfsm_i

gt2_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt2_rxuserrdy_i

gt2_rxuserrdy_i std_logic

Signal

gt2_rxuserrdy_t

gt2_rxuserrdy_t std_logic

Signal

gt2_tx_phalignment_done_i

gt2_tx_phalignment_done_i std_logic

Signal

gt2_txdlyen_i

gt2_txdlyen_i std_logic

Signal

gt2_txdlysreset_i

gt2_txdlysreset_i std_logic

Signal

gt2_txdlysresetdone_i

gt2_txdlysresetdone_i std_logic

Signal

gt2_txoutclk_i

gt2_txoutclk_i std_logic

Signal

gt2_txoutclk_i2

gt2_txoutclk_i2 std_logic

Signal

gt2_txphalign_i

gt2_txphalign_i std_logic

Signal

gt2_txphaligndone_i

gt2_txphaligndone_i std_logic

Signal

gt2_txphalignen_i

gt2_txphalignen_i std_logic

Signal

gt2_txphdlyreset_i

gt2_txphdlyreset_i std_logic

Signal

gt2_txphinit_i

gt2_txphinit_i std_logic

Signal

gt2_txphinitdone_i

gt2_txphinitdone_i std_logic

Signal

gt2_txpmaresetdone_i

gt2_txpmaresetdone_i std_logic

Signal

gt2_txresetdone_i

gt2_txresetdone_i std_logic

Signal

gt2_txresetdone_ii

gt2_txresetdone_ii std_logic

Signal

gt2_txresetfsm_i

gt2_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt2_txuserrdy_i

gt2_txuserrdy_i std_logic

Signal

gt2_txuserrdy_t

gt2_txuserrdy_t std_logic

Signal

gt3_gtrxreset_i

gt3_gtrxreset_i std_logic

Signal

gt3_gtrxreset_t

gt3_gtrxreset_t std_logic

Signal

gt3_gttxreset_i

gt3_gttxreset_i std_logic

Signal

gt3_gttxreset_t

gt3_gttxreset_t std_logic

Signal

gt3_recclk_stable_i

gt3_recclk_stable_i std_logic

Signal

gt3_rst_rx_phalignment_i

gt3_rst_rx_phalignment_i std_logic

Signal

gt3_rst_tx_phalignment_i

gt3_rst_tx_phalignment_i std_logic

Signal

gt3_run_rx_phalignment_i

gt3_run_rx_phalignment_i std_logic

Signal

gt3_run_tx_phalignment_i

gt3_run_tx_phalignment_i std_logic

Signal

gt3_rx_cdrlock_counter

gt3_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt3_rx_cdrlocked

gt3_rx_cdrlocked std_logic

Signal

gt3_rx_phalignment_done_i

gt3_rx_phalignment_done_i std_logic

Signal

gt3_rxdfeagchold_i

gt3_rxdfeagchold_i std_logic

Signal

gt3_rxdfelfhold_i

gt3_rxdfelfhold_i std_logic

Signal

gt3_rxdfelpmreset_i

gt3_rxdfelpmreset_i std_logic

Signal

gt3_rxdlyen_i

gt3_rxdlyen_i std_logic

Signal

gt3_rxdlysreset_i

gt3_rxdlysreset_i std_logic

Signal

gt3_rxdlysresetdone_i

gt3_rxdlysresetdone_i std_logic

Signal

gt3_rxlpmhfhold_i

gt3_rxlpmhfhold_i std_logic

Signal

gt3_rxlpmlfhold_i

gt3_rxlpmlfhold_i std_logic

Signal

gt3_rxoutclk_i

gt3_rxoutclk_i std_logic

Signal

gt3_rxoutclk_i2

gt3_rxoutclk_i2 std_logic

Signal

gt3_rxphalign_i

gt3_rxphalign_i std_logic

Signal

gt3_rxphaligndone_i

gt3_rxphaligndone_i std_logic

Signal

gt3_rxphalignen_i

gt3_rxphalignen_i std_logic

Signal

gt3_rxphdlyreset_i

gt3_rxphdlyreset_i std_logic

Signal

gt3_rxpmaresetdone_i

gt3_rxpmaresetdone_i std_logic

Signal

gt3_rxresetdone_i

gt3_rxresetdone_i std_logic

Signal

gt3_rxresetdone_ii

gt3_rxresetdone_ii std_logic

Signal

gt3_rxresetfsm_i

gt3_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt3_rxuserrdy_i

gt3_rxuserrdy_i std_logic

Signal

gt3_rxuserrdy_t

gt3_rxuserrdy_t std_logic

Signal

gt3_tx_phalignment_done_i

gt3_tx_phalignment_done_i std_logic

Signal

gt3_txdlyen_i

gt3_txdlyen_i std_logic

Signal

gt3_txdlysreset_i

gt3_txdlysreset_i std_logic

Signal

gt3_txdlysresetdone_i

gt3_txdlysresetdone_i std_logic

Signal

gt3_txoutclk_i

gt3_txoutclk_i std_logic

Signal

gt3_txoutclk_i2

gt3_txoutclk_i2 std_logic

Signal

gt3_txphalign_i

gt3_txphalign_i std_logic

Signal

gt3_txphaligndone_i

gt3_txphaligndone_i std_logic

Signal

gt3_txphalignen_i

gt3_txphalignen_i std_logic

Signal

gt3_txphdlyreset_i

gt3_txphdlyreset_i std_logic

Signal

gt3_txphinit_i

gt3_txphinit_i std_logic

Signal

gt3_txphinitdone_i

gt3_txphinitdone_i std_logic

Signal

gt3_txpmaresetdone_i

gt3_txpmaresetdone_i std_logic

Signal

gt3_txresetdone_i

gt3_txresetdone_i std_logic

Signal

gt3_txresetdone_ii

gt3_txresetdone_ii std_logic

Signal

gt3_txresetfsm_i

gt3_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt3_txuserrdy_i

gt3_txuserrdy_i std_logic

Signal

gt3_txuserrdy_t

gt3_txuserrdy_t std_logic

Signal

gt4_gtrxreset_i

gt4_gtrxreset_i std_logic

Signal

gt4_gtrxreset_t

gt4_gtrxreset_t std_logic

Signal

gt4_gttxreset_i

gt4_gttxreset_i std_logic

Signal

gt4_gttxreset_t

gt4_gttxreset_t std_logic

Signal

gt4_recclk_stable_i

gt4_recclk_stable_i std_logic

Signal

gt4_rst_rx_phalignment_i

gt4_rst_rx_phalignment_i std_logic

Signal

gt4_rst_tx_phalignment_i

gt4_rst_tx_phalignment_i std_logic

Signal

gt4_run_rx_phalignment_i

gt4_run_rx_phalignment_i std_logic

Signal

gt4_run_tx_phalignment_i

gt4_run_tx_phalignment_i std_logic

Signal

gt4_rx_cdrlock_counter

gt4_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt4_rx_cdrlocked

gt4_rx_cdrlocked std_logic

Signal

gt4_rx_manual_phase_i

gt4_rx_manual_phase_i CON_2Quads_6g4_RX_MANUAL_PHASE_ALIGN

Instantiation

gt4_rx_phalignment_done_i

gt4_rx_phalignment_done_i std_logic

Signal

gt4_rxdfeagchold_i

gt4_rxdfeagchold_i std_logic

Signal

gt4_rxdfelfhold_i

gt4_rxdfelfhold_i std_logic

Signal

gt4_rxdfelpmreset_i

gt4_rxdfelpmreset_i std_logic

Signal

gt4_rxdlyen_i

gt4_rxdlyen_i std_logic

Signal

gt4_rxdlysreset_i

gt4_rxdlysreset_i std_logic

Signal

gt4_rxdlysresetdone_i

gt4_rxdlysresetdone_i std_logic

Signal

gt4_rxlpmhfhold_i

gt4_rxlpmhfhold_i std_logic

Signal

gt4_rxlpmlfhold_i

gt4_rxlpmlfhold_i std_logic

Signal

gt4_rxoutclk_i

gt4_rxoutclk_i std_logic

Signal

gt4_rxoutclk_i2

gt4_rxoutclk_i2 std_logic

Signal

gt4_rxphalign_i

gt4_rxphalign_i std_logic

Signal

gt4_rxphaligndone_i

gt4_rxphaligndone_i std_logic

Signal

gt4_rxphalignen_i

gt4_rxphalignen_i std_logic

Signal

gt4_rxphdlyreset_i

gt4_rxphdlyreset_i std_logic

Signal

gt4_rxpmaresetdone_i

gt4_rxpmaresetdone_i std_logic

Signal

gt4_rxresetdone_i

gt4_rxresetdone_i std_logic

Signal

gt4_rxresetdone_ii

gt4_rxresetdone_ii std_logic

Signal

gt4_rxresetfsm_i

gt4_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt4_rxuserrdy_i

gt4_rxuserrdy_i std_logic

Signal

gt4_rxuserrdy_t

gt4_rxuserrdy_t std_logic

Signal

gt4_tx_manual_phase_i

gt4_tx_manual_phase_i CON_2Quads_6g4_TX_MANUAL_PHASE_ALIGN

Instantiation

gt4_tx_phalignment_done_i

gt4_tx_phalignment_done_i std_logic

Signal

gt4_txdlyen_i

gt4_txdlyen_i std_logic

Signal

gt4_txdlysreset_i

gt4_txdlysreset_i std_logic

Signal

gt4_txdlysresetdone_i

gt4_txdlysresetdone_i std_logic

Signal

gt4_txoutclk_i

gt4_txoutclk_i std_logic

Signal

gt4_txoutclk_i2

gt4_txoutclk_i2 std_logic

Signal

gt4_txphalign_i

gt4_txphalign_i std_logic

Signal

gt4_txphaligndone_i

gt4_txphaligndone_i std_logic

Signal

gt4_txphalignen_i

gt4_txphalignen_i std_logic

Signal

gt4_txphdlyreset_i

gt4_txphdlyreset_i std_logic

Signal

gt4_txphinit_i

gt4_txphinit_i std_logic

Signal

gt4_txphinitdone_i

gt4_txphinitdone_i std_logic

Signal

gt4_txpmaresetdone_i

gt4_txpmaresetdone_i std_logic

Signal

gt4_txresetdone_i

gt4_txresetdone_i std_logic

Signal

gt4_txresetdone_ii

gt4_txresetdone_ii std_logic

Signal

gt4_txresetfsm_i

gt4_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt4_txuserrdy_i

gt4_txuserrdy_i std_logic

Signal

gt4_txuserrdy_t

gt4_txuserrdy_t std_logic

Signal

gt5_gtrxreset_i

gt5_gtrxreset_i std_logic

Signal

gt5_gtrxreset_t

gt5_gtrxreset_t std_logic

Signal

gt5_gttxreset_i

gt5_gttxreset_i std_logic

Signal

gt5_gttxreset_t

gt5_gttxreset_t std_logic

Signal

gt5_recclk_stable_i

gt5_recclk_stable_i std_logic

Signal

gt5_rst_rx_phalignment_i

gt5_rst_rx_phalignment_i std_logic

Signal

gt5_rst_tx_phalignment_i

gt5_rst_tx_phalignment_i std_logic

Signal

gt5_run_rx_phalignment_i

gt5_run_rx_phalignment_i std_logic

Signal

gt5_run_tx_phalignment_i

gt5_run_tx_phalignment_i std_logic

Signal

gt5_rx_cdrlock_counter

gt5_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt5_rx_cdrlocked

gt5_rx_cdrlocked std_logic

Signal

gt5_rx_phalignment_done_i

gt5_rx_phalignment_done_i std_logic

Signal

gt5_rxdfeagchold_i

gt5_rxdfeagchold_i std_logic

Signal

gt5_rxdfelfhold_i

gt5_rxdfelfhold_i std_logic

Signal

gt5_rxdfelpmreset_i

gt5_rxdfelpmreset_i std_logic

Signal

gt5_rxdlyen_i

gt5_rxdlyen_i std_logic

Signal

gt5_rxdlysreset_i

gt5_rxdlysreset_i std_logic

Signal

gt5_rxdlysresetdone_i

gt5_rxdlysresetdone_i std_logic

Signal

gt5_rxlpmhfhold_i

gt5_rxlpmhfhold_i std_logic

Signal

gt5_rxlpmlfhold_i

gt5_rxlpmlfhold_i std_logic

Signal

gt5_rxoutclk_i

gt5_rxoutclk_i std_logic

Signal

gt5_rxoutclk_i2

gt5_rxoutclk_i2 std_logic

Signal

gt5_rxphalign_i

gt5_rxphalign_i std_logic

Signal

gt5_rxphaligndone_i

gt5_rxphaligndone_i std_logic

Signal

gt5_rxphalignen_i

gt5_rxphalignen_i std_logic

Signal

gt5_rxphdlyreset_i

gt5_rxphdlyreset_i std_logic

Signal

gt5_rxpmaresetdone_i

gt5_rxpmaresetdone_i std_logic

Signal

gt5_rxresetdone_i

gt5_rxresetdone_i std_logic

Signal

gt5_rxresetdone_ii

gt5_rxresetdone_ii std_logic

Signal

gt5_rxresetfsm_i

gt5_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt5_rxuserrdy_i

gt5_rxuserrdy_i std_logic

Signal

gt5_rxuserrdy_t

gt5_rxuserrdy_t std_logic

Signal

gt5_tx_phalignment_done_i

gt5_tx_phalignment_done_i std_logic

Signal

gt5_txdlyen_i

gt5_txdlyen_i std_logic

Signal

gt5_txdlysreset_i

gt5_txdlysreset_i std_logic

Signal

gt5_txdlysresetdone_i

gt5_txdlysresetdone_i std_logic

Signal

gt5_txoutclk_i

gt5_txoutclk_i std_logic

Signal

gt5_txoutclk_i2

gt5_txoutclk_i2 std_logic

Signal

gt5_txphalign_i

gt5_txphalign_i std_logic

Signal

gt5_txphaligndone_i

gt5_txphaligndone_i std_logic

Signal

gt5_txphalignen_i

gt5_txphalignen_i std_logic

Signal

gt5_txphdlyreset_i

gt5_txphdlyreset_i std_logic

Signal

gt5_txphinit_i

gt5_txphinit_i std_logic

Signal

gt5_txphinitdone_i

gt5_txphinitdone_i std_logic

Signal

gt5_txpmaresetdone_i

gt5_txpmaresetdone_i std_logic

Signal

gt5_txresetdone_i

gt5_txresetdone_i std_logic

Signal

gt5_txresetdone_ii

gt5_txresetdone_ii std_logic

Signal

gt5_txresetfsm_i

gt5_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt5_txuserrdy_i

gt5_txuserrdy_i std_logic

Signal

gt5_txuserrdy_t

gt5_txuserrdy_t std_logic

Signal

gt6_gtrxreset_i

gt6_gtrxreset_i std_logic

Signal

gt6_gtrxreset_t

gt6_gtrxreset_t std_logic

Signal

gt6_gttxreset_i

gt6_gttxreset_i std_logic

Signal

gt6_gttxreset_t

gt6_gttxreset_t std_logic

Signal

gt6_recclk_stable_i

gt6_recclk_stable_i std_logic

Signal

gt6_rst_rx_phalignment_i

gt6_rst_rx_phalignment_i std_logic

Signal

gt6_rst_tx_phalignment_i

gt6_rst_tx_phalignment_i std_logic

Signal

gt6_run_rx_phalignment_i

gt6_run_rx_phalignment_i std_logic

Signal

gt6_run_tx_phalignment_i

gt6_run_tx_phalignment_i std_logic

Signal

gt6_rx_cdrlock_counter

gt6_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt6_rx_cdrlocked

gt6_rx_cdrlocked std_logic

Signal

gt6_rx_phalignment_done_i

gt6_rx_phalignment_done_i std_logic

Signal

gt6_rxdfeagchold_i

gt6_rxdfeagchold_i std_logic

Signal

gt6_rxdfelfhold_i

gt6_rxdfelfhold_i std_logic

Signal

gt6_rxdfelpmreset_i

gt6_rxdfelpmreset_i std_logic

Signal

gt6_rxdlyen_i

gt6_rxdlyen_i std_logic

Signal

gt6_rxdlysreset_i

gt6_rxdlysreset_i std_logic

Signal

gt6_rxdlysresetdone_i

gt6_rxdlysresetdone_i std_logic

Signal

gt6_rxlpmhfhold_i

gt6_rxlpmhfhold_i std_logic

Signal

gt6_rxlpmlfhold_i

gt6_rxlpmlfhold_i std_logic

Signal

gt6_rxoutclk_i

gt6_rxoutclk_i std_logic

Signal

gt6_rxoutclk_i2

gt6_rxoutclk_i2 std_logic

Signal

gt6_rxphalign_i

gt6_rxphalign_i std_logic

Signal

gt6_rxphaligndone_i

gt6_rxphaligndone_i std_logic

Signal

gt6_rxphalignen_i

gt6_rxphalignen_i std_logic

Signal

gt6_rxphdlyreset_i

gt6_rxphdlyreset_i std_logic

Signal

gt6_rxpmaresetdone_i

gt6_rxpmaresetdone_i std_logic

Signal

gt6_rxresetdone_i

gt6_rxresetdone_i std_logic

Signal

gt6_rxresetdone_ii

gt6_rxresetdone_ii std_logic

Signal

gt6_rxresetfsm_i

gt6_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt6_rxuserrdy_i

gt6_rxuserrdy_i std_logic

Signal

gt6_rxuserrdy_t

gt6_rxuserrdy_t std_logic

Signal

gt6_tx_phalignment_done_i

gt6_tx_phalignment_done_i std_logic

Signal

gt6_txdlyen_i

gt6_txdlyen_i std_logic

Signal

gt6_txdlysreset_i

gt6_txdlysreset_i std_logic

Signal

gt6_txdlysresetdone_i

gt6_txdlysresetdone_i std_logic

Signal

gt6_txoutclk_i

gt6_txoutclk_i std_logic

Signal

gt6_txoutclk_i2

gt6_txoutclk_i2 std_logic

Signal

gt6_txphalign_i

gt6_txphalign_i std_logic

Signal

gt6_txphaligndone_i

gt6_txphaligndone_i std_logic

Signal

gt6_txphalignen_i

gt6_txphalignen_i std_logic

Signal

gt6_txphdlyreset_i

gt6_txphdlyreset_i std_logic

Signal

gt6_txphinit_i

gt6_txphinit_i std_logic

Signal

gt6_txphinitdone_i

gt6_txphinitdone_i std_logic

Signal

gt6_txpmaresetdone_i

gt6_txpmaresetdone_i std_logic

Signal

gt6_txresetdone_i

gt6_txresetdone_i std_logic

Signal

gt6_txresetdone_ii

gt6_txresetdone_ii std_logic

Signal

gt6_txresetfsm_i

gt6_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt6_txuserrdy_i

gt6_txuserrdy_i std_logic

Signal

gt6_txuserrdy_t

gt6_txuserrdy_t std_logic

Signal

gt7_gtrxreset_i

gt7_gtrxreset_i std_logic

Signal

gt7_gtrxreset_t

gt7_gtrxreset_t std_logic

Signal

gt7_gttxreset_i

gt7_gttxreset_i std_logic

Signal

gt7_gttxreset_t

gt7_gttxreset_t std_logic

Signal

gt7_recclk_stable_i

gt7_recclk_stable_i std_logic

Signal

gt7_rst_rx_phalignment_i

gt7_rst_rx_phalignment_i std_logic

Signal

gt7_rst_tx_phalignment_i

gt7_rst_tx_phalignment_i std_logic

Signal

gt7_run_rx_phalignment_i

gt7_run_rx_phalignment_i std_logic

Signal

gt7_run_tx_phalignment_i

gt7_run_tx_phalignment_i std_logic

Signal

gt7_rx_cdrlock_counter

gt7_rx_cdrlock_counter integer range 0 to WAIT_TIME_CDRLOCK := 0

Signal

gt7_rx_cdrlocked

gt7_rx_cdrlocked std_logic

Signal

gt7_rx_phalignment_done_i

gt7_rx_phalignment_done_i std_logic

Signal

gt7_rxdfeagchold_i

gt7_rxdfeagchold_i std_logic

Signal

gt7_rxdfelfhold_i

gt7_rxdfelfhold_i std_logic

Signal

gt7_rxdfelpmreset_i

gt7_rxdfelpmreset_i std_logic

Signal

gt7_rxdlyen_i

gt7_rxdlyen_i std_logic

Signal

gt7_rxdlysreset_i

gt7_rxdlysreset_i std_logic

Signal

gt7_rxdlysresetdone_i

gt7_rxdlysresetdone_i std_logic

Signal

gt7_rxlpmhfhold_i

gt7_rxlpmhfhold_i std_logic

Signal

gt7_rxlpmlfhold_i

gt7_rxlpmlfhold_i std_logic

Signal

gt7_rxoutclk_i

gt7_rxoutclk_i std_logic

Signal

gt7_rxoutclk_i2

gt7_rxoutclk_i2 std_logic

Signal

gt7_rxphalign_i

gt7_rxphalign_i std_logic

Signal

gt7_rxphaligndone_i

gt7_rxphaligndone_i std_logic

Signal

gt7_rxphalignen_i

gt7_rxphalignen_i std_logic

Signal

gt7_rxphdlyreset_i

gt7_rxphdlyreset_i std_logic

Signal

gt7_rxpmaresetdone_i

gt7_rxpmaresetdone_i std_logic

Signal

gt7_rxresetdone_i

gt7_rxresetdone_i std_logic

Signal

gt7_rxresetdone_ii

gt7_rxresetdone_ii std_logic

Signal

gt7_rxresetfsm_i

gt7_rxresetfsm_i CON_2Quads_6g4_RX_STARTUP_FSM

Instantiation

gt7_rxuserrdy_i

gt7_rxuserrdy_i std_logic

Signal

gt7_rxuserrdy_t

gt7_rxuserrdy_t std_logic

Signal

gt7_tx_phalignment_done_i

gt7_tx_phalignment_done_i std_logic

Signal

gt7_txdlyen_i

gt7_txdlyen_i std_logic

Signal

gt7_txdlysreset_i

gt7_txdlysreset_i std_logic

Signal

gt7_txdlysresetdone_i

gt7_txdlysresetdone_i std_logic

Signal

gt7_txoutclk_i

gt7_txoutclk_i std_logic

Signal

gt7_txoutclk_i2

gt7_txoutclk_i2 std_logic

Signal

gt7_txphalign_i

gt7_txphalign_i std_logic

Signal

gt7_txphaligndone_i

gt7_txphaligndone_i std_logic

Signal

gt7_txphalignen_i

gt7_txphalignen_i std_logic

Signal

gt7_txphdlyreset_i

gt7_txphdlyreset_i std_logic

Signal

gt7_txphinit_i

gt7_txphinit_i std_logic

Signal

gt7_txphinitdone_i

gt7_txphinitdone_i std_logic

Signal

gt7_txpmaresetdone_i

gt7_txpmaresetdone_i std_logic

Signal

gt7_txresetdone_i

gt7_txresetdone_i std_logic

Signal

gt7_txresetdone_ii

gt7_txresetdone_ii std_logic

Signal

gt7_txresetfsm_i

gt7_txresetfsm_i CON_2Quads_6g4_TX_STARTUP_FSM

Instantiation

gt7_txuserrdy_i

gt7_txuserrdy_i std_logic

Signal

gt7_txuserrdy_t

gt7_txuserrdy_t std_logic

Signal

mstr0_txsyncallin_i

mstr0_txsyncallin_i std_logic

Signal

mstr4_txsyncallin_i

mstr4_txsyncallin_i std_logic

Signal

RX_CDRLOCK_TIME

RX_CDRLOCK_TIME integer := get_cdrlock_time ( EXAMPLE_SIMULATION )

Constant

rx_cdrlocked

rx_cdrlocked std_logic

Signal

rxmstr0_rxsyncallin_i

rxmstr0_rxsyncallin_i std_logic

Signal

rxmstr4_rxsyncallin_i

rxmstr4_rxsyncallin_i std_logic

Signal

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

U0_rst_rx_phalignment_i

U0_rst_rx_phalignment_i std_logic

Signal

U0_rst_tx_phalignment_i

U0_rst_tx_phalignment_i std_logic

Signal

U0_run_rx_phalignment_i

U0_run_rx_phalignment_i std_logic

Signal

U0_run_tx_phalignment_i

U0_run_tx_phalignment_i std_logic

Signal

U0_RXDLYEN

U0_RXDLYEN std_logic_vector ( 3 downto 0 )

Signal

U0_RXDLYSRESET

U0_RXDLYSRESET std_logic_vector ( 3 downto 0 )

Signal

U0_RXDLYSRESETDONE

U0_RXDLYSRESETDONE std_logic_vector ( 3 downto 0 )

Signal

U0_RXPHALIGN

U0_RXPHALIGN std_logic_vector ( 3 downto 0 )

Signal

U0_RXPHALIGNDONE

U0_RXPHALIGNDONE std_logic_vector ( 3 downto 0 )

Signal

U0_TXDLYEN

U0_TXDLYEN std_logic_vector ( 3 downto 0 )

Signal

U0_TXDLYSRESET

U0_TXDLYSRESET std_logic_vector ( 3 downto 0 )

Signal

U0_TXDLYSRESETDONE

U0_TXDLYSRESETDONE std_logic_vector ( 3 downto 0 )

Signal

U0_TXPHALIGN

U0_TXPHALIGN std_logic_vector ( 3 downto 0 )

Signal

U0_TXPHALIGNDONE

U0_TXPHALIGNDONE std_logic_vector ( 3 downto 0 )

Signal

U0_TXPHINIT

U0_TXPHINIT std_logic_vector ( 3 downto 0 )

Signal

U0_TXPHINITDONE

U0_TXPHINITDONE std_logic_vector ( 3 downto 0 )

Signal

U4_rst_rx_phalignment_i

U4_rst_rx_phalignment_i std_logic

Signal

U4_rst_tx_phalignment_i

U4_rst_tx_phalignment_i std_logic

Signal

U4_run_rx_phalignment_i

U4_run_rx_phalignment_i std_logic

Signal

U4_run_tx_phalignment_i

U4_run_tx_phalignment_i std_logic

Signal

U4_RXDLYEN

U4_RXDLYEN std_logic_vector ( 3 downto 0 )

Signal

U4_RXDLYSRESET

U4_RXDLYSRESET std_logic_vector ( 3 downto 0 )

Signal

U4_RXDLYSRESETDONE

U4_RXDLYSRESETDONE std_logic_vector ( 3 downto 0 )

Signal

U4_RXPHALIGN

U4_RXPHALIGN std_logic_vector ( 3 downto 0 )

Signal

U4_RXPHALIGNDONE

U4_RXPHALIGNDONE std_logic_vector ( 3 downto 0 )

Signal

U4_TXDLYEN

U4_TXDLYEN std_logic_vector ( 3 downto 0 )

Signal

U4_TXDLYSRESET

U4_TXDLYSRESET std_logic_vector ( 3 downto 0 )

Signal

U4_TXDLYSRESETDONE

U4_TXDLYSRESETDONE std_logic_vector ( 3 downto 0 )

Signal

U4_TXPHALIGN

U4_TXPHALIGN std_logic_vector ( 3 downto 0 )

Signal

U4_TXPHALIGNDONE

U4_TXPHALIGNDONE std_logic_vector ( 3 downto 0 )

Signal

U4_TXPHINIT

U4_TXPHINIT std_logic_vector ( 3 downto 0 )

Signal

U4_TXPHINITDONE

U4_TXPHINITDONE std_logic_vector ( 3 downto 0 )

Signal

WAIT_TIME_CDRLOCK

WAIT_TIME_CDRLOCK integer := RX_CDRLOCK_TIME / STABLE_CLOCK_PERIOD

Constant

---

The documentation for this class was generated from the following file:

• IP/CON_2Quads_6g4/con_2quads_6g4_init.vhd