RTL Architecture Reference

Processes
PROCESS_527	( STABLE_CLOCK )
PROCESS_528	( STABLE_CLOCK )
PROCESS_529	( STABLE_CLOCK )
PROCESS_530	( STABLE_CLOCK )

Components
DSS_3Quads_11g2_sync_block	<Entity DSS_3Quads_11g2_sync_block>
DSS_3Quads_11g2_sync_pulse	<Entity DSS_3Quads_11g2_sync_pulse>

Constants
VCC_VEC	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 1 ' )
GND_VEC	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Types
tx_phase_align_manual_fsm	( INIT , WAIT_PHRST_DONE , M_PHINIT , M_PHALIGN , M_DLYEN , S_PHINIT , S_PHALIGN , M_DLYEN2 , PHALIGN_DONE )

Signals
txphaligndone_prev	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
txphaligndone_ris_edge	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 )
txphinitdone_prev	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
txphinitdone_ris_edge	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 )
txphinitdone_store_edge	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
txphinitdone_clear_slave	std_logic := ' 0 '
txdlysresetdone_store	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
txphaligndone_store	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
txdone_clear	std_logic := ' 0 '
txphaligndone_sync	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
txphinitdone_sync	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
txdlysresetdone_sync	std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )
tx_phalign_manual_state	tx_phase_align_manual_fsm := INIT

Instantiations
sync_txphaligndone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_txdlysresetdone	DSS_3Quads_11g2_sync_block <Entity DSS_3Quads_11g2_sync_block>
sync_txphinitdone	DSS_3Quads_11g2_sync_pulse <Entity DSS_3Quads_11g2_sync_pulse>

Member Function Documentation

PROCESS_527()

PROCESS_527

(

STABLE_CLOCK

)

PROCESS_528()

PROCESS_528 (   STABLE_CLOCK   )

Process

PROCESS_529()

PROCESS_529 (   STABLE_CLOCK   )

Process

PROCESS_530()

PROCESS_530 (   STABLE_CLOCK   )

Process

Member Data Documentation

DSS_3Quads_11g2_sync_block

DSS_3Quads_11g2_sync_block

Component

DSS_3Quads_11g2_sync_pulse

DSS_3Quads_11g2_sync_pulse

Component

GND_VEC

GND_VEC std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Constant

sync_txdlysresetdone

sync_txdlysresetdone DSS_3Quads_11g2_sync_block

Instantiation

sync_txphaligndone

sync_txphaligndone DSS_3Quads_11g2_sync_block

Instantiation

sync_txphinitdone

sync_txphinitdone DSS_3Quads_11g2_sync_pulse

Instantiation

tx_phalign_manual_state

tx_phalign_manual_state tx_phase_align_manual_fsm := INIT

Signal

tx_phase_align_manual_fsm

tx_phase_align_manual_fsm ( INIT , WAIT_PHRST_DONE , M_PHINIT , M_PHALIGN , M_DLYEN , S_PHINIT , S_PHALIGN , M_DLYEN2 , PHALIGN_DONE )

Type

txdlysresetdone_store

txdlysresetdone_store std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

txdlysresetdone_sync

txdlysresetdone_sync std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

txdone_clear

txdone_clear std_logic := ' 0 '

Signal

txphaligndone_prev

txphaligndone_prev std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

txphaligndone_ris_edge

txphaligndone_ris_edge std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 )

Signal

txphaligndone_store

txphaligndone_store std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

txphaligndone_sync

txphaligndone_sync std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

txphinitdone_clear_slave

txphinitdone_clear_slave std_logic := ' 0 '

Signal

txphinitdone_prev

txphinitdone_prev std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

txphinitdone_ris_edge

txphinitdone_ris_edge std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 )

Signal

txphinitdone_store_edge

txphinitdone_store_edge std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

txphinitdone_sync

txphinitdone_sync std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

VCC_VEC

VCC_VEC std_logic_vector ( NUMBER_OF_LANES - 1 downto 0 ) := ( others = > ' 1 ' )

Constant

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The documentation for this class was generated from the following file:

• IP/DSS_3Quads_11g2/DSS_3Quads_11g2/example_design/dss_3quads_11g2_tx_manual_phase_align.vhd