rtl Architecture Reference

Processes
PROCESS_483	( clk )

Signals
ack	std_logic
addr	std_logic_vector ( 2 downto 0 )
pointer_creg	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
zero_pointer_int	std_logic := ' 0 '
spin_pointer_int	std_logic := ' 0 '
max_value	std_logic_vector ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 1 ' )
pointer_value	std_logic_vector ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
loadin_sig	std_logic
fine_delay	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Instantiations
clock_to_signal	clock_pulse <Entity clock_pulse>
source_pointer	algo_pointer <Entity algo_pointer>

Member Function Documentation

PROCESS_483()

PROCESS_483

(

clk

)

Member Data Documentation

ack

ack std_logic

Signal

addr

addr std_logic_vector ( 2 downto 0 )

Signal

clock_to_signal

clock_to_signal clock_pulse

Instantiation

fine_delay

fine_delay std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Signal

loadin_sig

loadin_sig std_logic

Signal

max_value

max_value std_logic_vector ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 1 ' )

Signal

pointer_creg

pointer_creg std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

pointer_value

pointer_value std_logic_vector ( ADDR_WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

source_pointer

source_pointer algo_pointer

Instantiation

spin_pointer_int

spin_pointer_int std_logic := ' 0 '

Signal

zero_pointer_int

zero_pointer_int std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/ipbus_algo_master_pointers.vhd