rtl Architecture Reference

Processes
PROCESS_296	( clk )
PROCESS_856	( clk )

Constants
ADDR_WIDTH	integer := integer_max ( calc_width ( N_CTRL ) , calc_width ( N_STAT ) )

Signals
sel	integer range 0 to 2 ** ADDR_WIDTH - 1 := 0
ctrl_cyc_w	std_logic
ctrl_cyc_r	std_logic
stat_cyc	std_logic
cq	ipb_reg_v ( 2 ** ADDR_WIDTH - 1 downto 0 )
sq	std_logic_vector ( 31 downto 0 )
ds	std_logic_vector ( 31 downto 0 )
cbusy	std_logic_vector ( N_CTRL - 1 downto 0 )
cack	std_logic_vector ( N_CTRL - 1 downto 0 )
sbusy	std_logic
sack	std_logic
sre	std_logic
busy	std_logic
ack	std_logic
busy_d	std_logic
pend	std_logic
cwe	std_logic
ctrl_m	std_logic_vector ( 31 downto 0 )

Instantiations
wsync	syncreg_w <Entity syncreg_w>
rsync	syncreg_r <Entity syncreg_r>
wsync	syncreg_w <Entity syncreg_w>
rsync	syncreg_r <Entity syncreg_r>

Member Function Documentation

PROCESS_296()

PROCESS_296

(

clk

)

PROCESS_856()

PROCESS_856

(

clk

)

Member Data Documentation

ack

ack std_logic

Signal

ADDR_WIDTH

ADDR_WIDTH integer := integer_max ( calc_width ( N_CTRL ) , calc_width ( N_STAT ) )

Constant

busy

busy std_logic

Signal

busy_d

busy_d std_logic

Signal

cack

cack std_logic_vector ( N_CTRL - 1 downto 0 )

Signal

cbusy

cbusy std_logic_vector ( N_CTRL - 1 downto 0 )

Signal

cq

cq ipb_reg_v ( 2 ** ADDR_WIDTH - 1 downto 0 )

Signal

ctrl_cyc_r

ctrl_cyc_r std_logic

Signal

ctrl_cyc_w

ctrl_cyc_w std_logic

Signal

ctrl_m

ctrl_m std_logic_vector ( 31 downto 0 )

Signal

cwe

cwe std_logic

Signal

ds

ds std_logic_vector ( 31 downto 0 )

Signal

pend

pend std_logic

Signal

rsync [1/2]

rsync syncreg_r

Instantiation

rsync [2/2]

rsync syncreg_r

Instantiation

sack

sack std_logic

Signal

sbusy

sbusy std_logic

Signal

sel

sel integer range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

sq

sq std_logic_vector ( 31 downto 0 )

Signal

sre

sre std_logic

Signal

stat_cyc

stat_cyc std_logic

Signal

wsync [1/2]

wsync syncreg_w

Instantiation

wsync [2/2]

wsync syncreg_w

Instantiation

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/ipbus_syncreg_v.vhd