rtl Architecture Reference

Processes
PROCESS_308	( sclk )
PROCESS_309	( sclk )
PROCESS_310	( clk )
PROCESS_311	( clk )
PROCESS_868	( sclk )
PROCESS_869	( sclk )
PROCESS_870	( clk )
PROCESS_871	( clk )

Components
sdpram_16x10_32x9	<Entity sdpram_16x10_32x9>
sdpram_32x9_16x10	<Entity sdpram_32x9_16x10>

Signals
samp_nwe	std_logic_vector ( 1 DOWNTO 0 ) := ( others = > ' 1 ' )
samp_nrd	std_logic_vector ( 1 DOWNTO 0 ) := ( others = > ' 1 ' )
ack	std_logic
we_pipe	std_logic_vector ( 0 downto 0 )
w_addr_pipe	unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )
w_data_pipe	std_logic_vector ( 15 downto 0 )
r_addr_ipbus	unsigned ( 8 downto 0 ) := ( others = > ' 0 ' )
r_data_ipbus	std_logic_vector ( 31 downto 0 )
we_ipbus	std_logic_vector ( 0 downto 0 )
w_addr_ipbus	unsigned ( 8 downto 0 ) := ( others = > ' 1 ' )
w_data_ipbus	std_logic_vector ( 31 downto 0 )
r_addr_pipe	unsigned ( 9 downto 0 ) := ( others = > ' 0 ' )
r_data_pipe	std_logic_vector ( 15 downto 0 )
pipe_to_ipbus_reset	std_logic
ipbus_to_pipe_reset	std_logic
we_pipe_clked	std_logic_vector ( 0 downto 0 )
uc_pipe_clked	std_logic_vector ( 15 downto 0 )
r_addr_pipe_ipb_domain	unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )
r_addr_pipe_sclk_domain	unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )
w_addr_pipe_ipb_domain	unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )
w_addr_pipe_sclk_domain	unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )

Instantiations
ram_pipe_to_ipbus	sdpram_16x10_32x9 <Entity sdpram_16x10_32x9>
ram_ipbus_to_pipe	sdpram_32x9_16x10 <Entity sdpram_32x9_16x10>
ram_pipe_to_ipbus	sdpram_16x10_32x9 <Entity sdpram_16x10_32x9>
ram_ipbus_to_pipe	sdpram_32x9_16x10 <Entity sdpram_32x9_16x10>

Member Function Documentation

PROCESS_308()

PROCESS_308 (   sclk   )

Process

PROCESS_309()

PROCESS_309 (   sclk   )

Process

PROCESS_310()

PROCESS_310 (   clk   )

Process

PROCESS_311()

PROCESS_311 (   clk   )

Process

PROCESS_868()

PROCESS_868 (   sclk   )

Process

PROCESS_869()

PROCESS_869 (   sclk   )

Process

PROCESS_870()

PROCESS_870 (   clk   )

Process

PROCESS_871()

PROCESS_871 (   clk   )

Process

Member Data Documentation

ack

ack std_logic

Signal

ipbus_to_pipe_reset

ipbus_to_pipe_reset std_logic

Signal

pipe_to_ipbus_reset

pipe_to_ipbus_reset std_logic

Signal

r_addr_ipbus

r_addr_ipbus unsigned ( 8 downto 0 ) := ( others = > ' 0 ' )

Signal

r_addr_pipe

r_addr_pipe unsigned ( 9 downto 0 ) := ( others = > ' 0 ' )

Signal

r_addr_pipe_ipb_domain

r_addr_pipe_ipb_domain unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )

Signal

r_addr_pipe_sclk_domain

r_addr_pipe_sclk_domain unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )

Signal

r_data_ipbus

r_data_ipbus std_logic_vector ( 31 downto 0 )

Signal

r_data_pipe

r_data_pipe std_logic_vector ( 15 downto 0 )

Signal

ram_ipbus_to_pipe [1/2]

ram_ipbus_to_pipe sdpram_32x9_16x10

Instantiation

ram_ipbus_to_pipe [2/2]

ram_ipbus_to_pipe sdpram_32x9_16x10

Instantiation

ram_pipe_to_ipbus [1/2]

ram_pipe_to_ipbus sdpram_16x10_32x9

Instantiation

ram_pipe_to_ipbus [2/2]

ram_pipe_to_ipbus sdpram_16x10_32x9

Instantiation

samp_nrd

samp_nrd std_logic_vector ( 1 DOWNTO 0 ) := ( others = > ' 1 ' )

Signal

samp_nwe

samp_nwe std_logic_vector ( 1 DOWNTO 0 ) := ( others = > ' 1 ' )

Signal

sdpram_16x10_32x9

sdpram_16x10_32x9

Component

sdpram_32x9_16x10

sdpram_32x9_16x10

Component

uc_pipe_clked

uc_pipe_clked std_logic_vector ( 15 downto 0 )

Signal

w_addr_ipbus

w_addr_ipbus unsigned ( 8 downto 0 ) := ( others = > ' 1 ' )

Signal

w_addr_pipe

w_addr_pipe unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )

Signal

w_addr_pipe_ipb_domain

w_addr_pipe_ipb_domain unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )

Signal

w_addr_pipe_sclk_domain

w_addr_pipe_sclk_domain unsigned ( 9 downto 0 ) := ( others = > ' 1 ' )

Signal

w_data_ipbus

w_data_ipbus std_logic_vector ( 31 downto 0 )

Signal

w_data_pipe

w_data_pipe std_logic_vector ( 15 downto 0 )

Signal

we_ipbus

we_ipbus std_logic_vector ( 0 downto 0 )

Signal

we_pipe

we_pipe std_logic_vector ( 0 downto 0 )

Signal

we_pipe_clked

we_pipe_clked std_logic_vector ( 0 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_slaves/firmware/hdl/uc_pipe_interface.vhd