ROD firmware  1.0.5
ATLAS l1-calo - ROD_eFEX and ROD_jFEX firmware for the L1Calo ROD board

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chan_err_map.vhd
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 13.10.2021 17:50:42
6 -- Design Name:
7 -- Module Name: chan_err_map - RTL
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 
21 
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 
25 -- Uncomment the following library declaration if using
26 -- arithmetic functions with Signed or Unsigned values
27 --use IEEE.NUMERIC_STD.ALL;
28 
29 -- Uncomment the following library declaration if instantiating
30 -- any Xilinx leaf cells in this code.
31 --library UNISIM;
32 --use UNISIM.VComponents.all;
33 
34 entity chan_err_map is
35  generic (
36  jfex : integer := 1
37  );
38  Port (
39  clock : in std_logic;
40  reset_0 : in std_logic;
41  reset_1 : in std_logic;
42  reset_2 : in std_logic;
43  reset_3 : in std_logic;
44  reset_4 : in std_logic;
45  error_0 : in std_logic;
46  error_1 : in std_logic;
47  error_2 : in std_logic;
48  error_3 : in std_logic;
49  error_4 : in std_logic;
50  sample_0 : in std_logic;
51  sample_1 : in std_logic;
52  sample_2 : in std_logic;
53  sample_3 : in std_logic;
54  sample_4 : in std_logic;
55  chan_in : in STD_LOGIC_VECTOR (4 downto 0) ;
56  error_map_0 : out STD_LOGIC_VECTOR (23 downto 0);
57  error_map_1 : out STD_LOGIC_VECTOR (23 downto 0);
58  error_map_2 : out STD_LOGIC_VECTOR (23 downto 0);
59  error_map_3 : out STD_LOGIC_VECTOR (23 downto 0);
60  error_map_4 : out STD_LOGIC_VECTOR (23 downto 0)
61  );
62 end chan_err_map;
63 
64 
65 architecture RTL of chan_err_map is
66 
67 --constant last_chan : integer := 23;
68 constant last_chan : integer := 23;
69 
70 --process begin
71 --if (jfex = '1') then
72 -- last_chan <= 23;
73 --else
74 -- last_chan<= 11;
75 --end if;
76 --end process;
77 
78 signal bit_sel : std_logic_vector (last_chan downto 0);
79 signal map_reg_0 : std_logic_vector (23 downto 0);
80 signal map_reg_1 : std_logic_vector (23 downto 0);
81 signal map_reg_2 : std_logic_vector (23 downto 0);
82 signal map_reg_3 : std_logic_vector (23 downto 0);
83 signal map_reg_4 : std_logic_vector (23 downto 0);
84 signal error_s_0 : std_logic;
85 signal error_s_1 : std_logic;
86 signal error_s_2 : std_logic;
87 signal error_s_3 : std_logic;
88 signal error_s_4 : std_logic;
89 signal reset_0_s : std_logic;
90 signal reset_1_s : std_logic;
91 signal reset_2_s : std_logic;
92 signal reset_3_s : std_logic;
93 signal reset_4_s : std_logic;
94 signal chan_in_s : std_logic_vector (4 downto 0);
95 
96 COMPONENT error_ila
97 PORT (
98  clk : IN STD_LOGIC;
99  probe0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
100  probe1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
101  probe2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
102  probe3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
103  probe4 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
104  probe5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
105  probe6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
106  probe7 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
107  probe8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
108  probe9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
109  probe10 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
110  probe11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
111  probe12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0)
112 );
113 end component;
114 
115 begin
116 
117 
118 
119 
120 --sync the reset inputs to pp_clk
121 
122 
123 --sync the reset inputs to pp_clk
124 process (clock) begin
125  if rising_edge (clock) then
126  reset_0_s <= reset_0;
127  reset_1_s <= reset_1;
128  reset_2_s <= reset_2;
129  reset_3_s <= reset_3;
130  reset_4_s <= reset_4;
131  end if;
132 end process;
133 
134 
135 --delay chan_in to fix alignment issue with crc20 error
136 process (clock) begin
137  if rising_edge (clock) then
138  chan_in_s <= chan_in;
139  end if;
140 end process;
141 
142 
143 --last_chan_set: if jfex=1 generate
144 -- last_chan := 23;
145 -- elsif jfex=0 generate
146 -- last_chan := 11;
147 -- end generate last_chan_set;
148 
149 with chan_in_s select
150  bit_sel <= x"000001" when 5x"0",
151  x"000002" when 5x"1",
152  x"000004" when 5x"2",
153  x"000008" when 5x"3",
154  x"000010" when 5x"4",
155  x"000020" when 5x"5",
156  x"000040" when 5x"6",
157  x"000080" when 5x"7",
158 
159  x"000100" when 5x"8",
160  x"000200" when 5x"9",
161  x"000400" when 5x"A",
162  x"000800" when 5x"B",
163  x"001000" when 5x"C",
164  x"002000" when 5x"D",
165  x"004000" when 5x"E",
166  x"008000" when 5x"F",
167 
168  x"010000" when 5x"10",
169  x"020000" when 5x"11",
170  x"040000" when 5x"12",
171  x"080000" when 5x"13",
172  x"100800" when 5x"14",
173  x"200000" when 5x"15",
174  x"400000" when 5x"16",
175  x"800000" when 5x"17",
176  x"000000" when others;
177 
178 error_map_0 <= map_reg_0;
179 error_map_1 <= map_reg_1;
180 error_map_2 <= map_reg_2;
181 error_map_3 <= map_reg_3;
182 error_map_4 <= map_reg_4;
183 
184 error_s_0 <= error_0 and sample_0;
185 error_s_1 <= error_1 and sample_1;
186 error_s_2 <= error_2 and sample_2;
187 error_s_3 <= error_3 and sample_3;
188 error_s_4 <= error_4 and sample_4;
189 
190 -----map register 0 ------
191 process (clock) begin
192  if rising_edge (clock) then
193  if reset_0_s = '1' then
194  map_reg_0 <= x"000000";
195  else
196  for I in 0 to 23 loop
197  if (bit_sel(I) = '1') and (error_s_0 = '1') then
198  map_reg_0(I) <= '1';
199  else map_reg_0(I) <= map_reg_0(I);
200  end if;
201  end loop;
202  end if ;
203  end if;
204 end process;
205 
206 
207 -----map register 1 ------
208 process (clock) begin
209  if rising_edge (clock) then
210  if reset_1_s = '1' then
211  map_reg_1 <= x"000000";
212  else
213  for I in 0 to 23 loop
214  if (bit_sel(I) = '1') and (error_s_1 = '1') then
215  map_reg_1(I) <= '1';
216  else map_reg_1(I) <= map_reg_1(I);
217  end if;
218  end loop;
219  end if ;
220  end if;
221 end process;
222 
223 -----map register 2 ------
224 process (clock) begin
225  if rising_edge (clock) then
226  if reset_2_s = '1' then
227  map_reg_2 <= x"000000";
228  else
229  for I in 0 to 23 loop
230  if (bit_sel(I) = '1') and (error_s_2 = '1') then
231  map_reg_2(I) <= '1';
232  else map_reg_2(I) <= map_reg_2(I);
233  end if;
234  end loop;
235  end if ;
236  end if;
237 end process;
238 
239 -----map register 3 ------
240 process (clock) begin
241  if rising_edge (clock) then
242  if reset_3_s = '1' then
243  map_reg_3 <= x"000000";
244  else
245  for I in 0 to 23 loop
246  if (bit_sel(I) = '1') and (error_s_3 = '1') then
247  map_reg_3(I) <= '1';
248  else map_reg_3(I) <= map_reg_3(I);
249  end if;
250  end loop;
251  end if ;
252  end if;
253 end process;
254 
255 
256 -----map register 4 ------
257 process (clock) begin
258  if rising_edge (clock) then
259  if reset_4_s = '1' then
260  map_reg_4 <= x"000000";
261  else
262  for I in 0 to 23 loop
263  if (bit_sel(I) = '1') and (error_s_4 = '1') then
264  map_reg_4(I) <= '1';
265  else map_reg_4(I) <= map_reg_4(I);
266  end if;
267  end loop;
268  end if ;
269  end if;
270 end process;
271 
272 
273 
274 --ILA removed to free up resources 12-oct-23
275 --error_map_ila : error_ila
276 -- port map (
277 -- clk => clock,
278 -- probe0 => bit_sel, --24-bit
279 -- probe1 => map_reg_4, --24-bit
280 -- probe2(0) => error_s_4, --1-bit
281 -- probe3(0) => reset_4_s, --1-bit
282 -- probe4 => map_reg_1, --24-bit
283 -- probe5(0) => error_s_1, --1-bit
284 -- probe6(0) => reset_1_s, --1-bit
285 -- probe7 => map_reg_2, --24-bit
286 -- probe8(0) => error_s_2, --1-bit
287 -- probe9(0) => reset_2_s, --1-bit
288 -- probe10 => map_reg_3, --24-bit
289 -- probe11(0) => error_s_3, --1-bit
290 -- probe12(0) => reset_3_s --1-bit
291 -- );
292 
293 
294 end RTL;
chan_err_map.RTL
Definition: chan_err_map.vhd:65
chan_err_map
Definition: chan_err_map.vhd:34
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